From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 19:50:21 +0000 (-0700)
Subject: wreduce for $sub
X-Git-Tag: working-ls180~1163^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc0e36d1c02c22a578020aa1f2c90c86844fefe6;p=yosys.git

wreduce for $sub
---

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 1fbc41082..e8c2cb726 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -365,6 +365,29 @@ struct WreduceWorker
 			}
 		}
 
+		if (cell->type.in("$add", "$sub")) {
+			SigSpec A = cell->getPort("\\A");
+			SigSpec B = cell->getPort("\\B");
+			bool sub = cell->type == "$sub";
+
+			int i;
+			for (i = 0; i < GetSize(sig); i++) {
+				if (B[i] != S0 && (sub || A[i] != S0))
+					break;
+				if (B[i] == S0)
+					module->connect(sig[i], A[i]);
+				else if (A[i] == S0)
+					module->connect(sig[i], B[i]);
+				else log_abort();
+			}
+			if (i > 0) {
+				cell->setPort("\\A", A.extract(i, -1));
+				cell->setPort("\\B", B.extract(i, -1));
+				sig.remove(0, i);
+				bits_removed += i;
+			}
+		}
+
 		if (GetSize(sig) == 0) {
 			log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
 			module->remove(cell);