From: H.J. Lu Date: Fri, 15 Dec 2006 14:09:22 +0000 (+0000) Subject: 2006-12-15 H.J. Lu X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc225355e8a67d38373dbced800eb2848723dc44;p=binutils-gdb.git 2006-12-15 H.J. Lu * config/tc-i386.c (build_modrm_byte): Reformat to 72 columns. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index dce27c0e84e..cbc3034e1e1 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2006-12-15 H.J. Lu + + * config/tc-i386.c (build_modrm_byte): Reformat to 72 columns. + 2006-12-14 Daniel Jacobowitz * Makefile.am (YFLAGS): Define. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 3b54ed5899c..d4bba26daa5 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3430,8 +3430,9 @@ build_modrm_byte () | Control | Debug | Test)) ? 0 : 1); - /* In 4 operands instructions with 2 immediate operands, the first two are immediate - bytes and hence source operand will be in the next byte after the immediates */ + /* In 4 operands instructions with 2 immediate operands, the first + two are immediate bytes and hence source operand will be in the + next byte after the immediates */ if ((i.operands == 4)&&(i.imm_operands=2)) source++; dest = source + 1; @@ -3496,9 +3497,11 @@ build_modrm_byte () i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; i.sib.base = NO_BASE_REGISTER; i.sib.index = NO_INDEX_REGISTER; - i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32); + i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) + ? Disp32S : Disp32); } - else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) + else if ((flag_code == CODE_16BIT) + ^ (i.prefix[ADDR_PREFIX] != 0)) { i.rm.regmem = NO_BASE_REGISTER_16; i.types[op] = Disp16; @@ -3568,7 +3571,9 @@ build_modrm_byte () { if (flag_code == CODE_64BIT && (i.types[op] & Disp)) - i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32); + i.types[op] = ((i.types[op] & Disp8) + | (i.prefix[ADDR_PREFIX] == 0 + ? Disp32S : Disp32)); i.rm.regmem = i.base_reg->reg_num; if ((i.base_reg->reg_flags & RegRex) != 0)