From: Tim Newsome <tim@sifive.com>
Date: Mon, 19 Feb 2018 21:31:40 +0000 (-0800)
Subject: Test debugging with/without a program buffer
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc3d7e8196dfb567a9b6c34dd97c1b43260b4cd5;p=riscv-tests.git

Test debugging with/without a program buffer
---

diff --git a/debug/Makefile b/debug/Makefile
index 8e1c81b..48be07c 100644
--- a/debug/Makefile
+++ b/debug/Makefile
@@ -4,7 +4,7 @@ XLEN ?= 64
 src_dir ?= .
 GDBSERVER_PY = $(src_dir)/gdbserver.py
 
-default: spike$(XLEN)-2
+default: spike$(XLEN) spike$(XLEN)-2
 
 all-tests: spike32 spike32-2 spike32-2-rtos spike64 spike64-2 spike64-2-rtos
 
diff --git a/debug/targets/RISC-V/spike32-2-rtos.py b/debug/targets/RISC-V/spike32-2-rtos.py
index a7b9a1c..79105d5 100644
--- a/debug/targets/RISC-V/spike32-2-rtos.py
+++ b/debug/targets/RISC-V/spike32-2-rtos.py
@@ -9,4 +9,4 @@ class spike32_2(targets.Target):
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, progbufsize=0)
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index f57f816..89d3c2a 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -9,4 +9,4 @@ class spike32_2(targets.Target):
     timeout_sec = 30
 
     def create(self):
-        return testlib.Spike(self, isa="RV32IMAFC")
+        return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0)
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index 2aa1dd0..d5802b5 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -16,4 +16,4 @@ class spike64(targets.Target):
 
     def create(self):
         # 32-bit FPRs only
-        return testlib.Spike(self, isa="RV64IMAFC")
+        return testlib.Spike(self, isa="RV64IMAFC", progbufsize=0)
diff --git a/debug/testlib.py b/debug/testlib.py
index 3aaa542..5c40a5d 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -57,11 +57,12 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin
 
 class Spike(object):
     def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True,
-            isa=None):
+            isa=None, progbufsize=None):
         """Launch spike. Return tuple of its process and the port it's running
         on."""
         self.process = None
         self.isa = isa
+        self.progbufsize = progbufsize
 
         if target.harts:
             harts = target.harts
@@ -118,6 +119,10 @@ class Spike(object):
 
         cmd += ["--isa", isa]
 
+        if not self.progbufsize is None:
+            cmd += ["--progsize", str(self.progbufsize)]
+            cmd += ["--debug-sba", "32"]
+
         assert len(set(t.ram for t in harts)) == 1, \
                 "All spike harts must have the same RAM layout"
         assert len(set(t.ram_size for t in harts)) == 1, \