From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 30 Apr 2021 13:05:01 +0000 (+0100)
Subject: add option to use new mmu_cache_wb ConfigMemoryPortInterface
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc41c3f7e70b6f17803d021a6f03d1043fb01874;p=soc.git

add option to use new mmu_cache_wb ConfigMemoryPortInterface
---

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 85a14869..108c9c77 100644
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -135,8 +135,11 @@ class TestRunner(FHDLTestCase):
         pc_i = Signal(32)
         svstate_i = Signal(32)
 
-        pspec = TestMemPspec(ldst_ifacetype='test_bare_wb',
-                             imem_ifacetype='test_bare_wb',
+        ldst_ifacetype = 'mmu_cache_wb' if microwatt_mmu else 'test_bare_wb'
+        imem_ifacetype = 'test_bare_wb'
+
+        pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
+                             imem_ifacetype=imem_ifacetype,
                              addr_wid=48,
                              mask_wid=8,
                              imem_reg_wid=64,