From: Paul Mackerras <paulus@ozlabs.org>
Date: Tue, 9 Aug 2022 09:48:30 +0000 (+1000)
Subject: writeback: Eliminate unintentional inferred latch
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc58559ee82178ba3fa1a82530bd381fa9eb55ba;p=microwatt.git

writeback: Eliminate unintentional inferred latch

By not assigning to interrupt_out.srr1 in some circumstances, the
writeback_1 process creates an inferred latch, which is not
desirable.  Eliminate it by restructuring the code so
interrupt_out.srr1 is always set, to zeroes if nothing else.

Fixes: bc4d02cb0dcc ("Start removing SPRs from register file", 2022-07-12)
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---

diff --git a/writeback.vhdl b/writeback.vhdl
index 2f6af2c..7fef5c3 100644
--- a/writeback.vhdl
+++ b/writeback.vhdl
@@ -92,21 +92,20 @@ begin
         intr := e_in.interrupt or l_in.interrupt or fp_in.interrupt;
         interrupt_out.intr <= intr;
 
-        if intr = '1' then
-            srr1 := (others => '0');
-            if e_in.interrupt = '1' then
-                vec := e_in.intr_vec;
-                srr1 := e_in.srr1;
-            elsif l_in.interrupt = '1' then
-                vec := l_in.intr_vec;
-                srr1 := l_in.srr1;
-            elsif fp_in.interrupt = '1' then
-                vec := fp_in.intr_vec;
-                srr1 := fp_in.srr1;
-            end if;
-            interrupt_out.srr1 <= srr1;
+        srr1 := (others => '0');
+        if e_in.interrupt = '1' then
+            vec := e_in.intr_vec;
+            srr1 := e_in.srr1;
+        elsif l_in.interrupt = '1' then
+            vec := l_in.intr_vec;
+            srr1 := l_in.srr1;
+        elsif fp_in.interrupt = '1' then
+            vec := fp_in.intr_vec;
+            srr1 := fp_in.srr1;
+        end if;
+        interrupt_out.srr1 <= srr1;
 
-        else
+        if intr = '0' then
             if e_in.write_enable = '1' then
                 w_out.write_reg <= e_in.write_reg;
                 w_out.write_data <= e_in.write_data;