From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Nov 2018 16:55:41 +0000 (+0000)
Subject: elwidth variant of rv_mulhu
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc5f273b57ff3a1b11e415b8a84602f1154d1ffc;p=riscv-isa-sim.git

elwidth variant of rv_mulhu
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index cfdc6dc..bf78ba9 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -605,7 +605,16 @@ sv_sreg_t sv_proc_t::rv_mul(sv_sreg_t const & lhs, sv_sreg_t const & rhs)
 /* 32-bit mulh/mulhu/mulhsu */
 sv_reg_t sv_proc_t::rv_mulhu(sv_reg_t const & lhs, sv_reg_t const & rhs)
 {
-    return rv_mul(lhs, rhs) >> 32;
+    sv_reg_t m = rv_mul(lhs, rhs);
+    uint8_t bitwidth = get_bitwidth(m.get_elwidth(), xlen);
+    uint64_t result = (uint64_t)m;
+    result >>= std::min(bitwidth, (uint8_t)32);
+    if (_insn->signextended) {
+        result = sext_bwid(result, bitwidth);
+    } else {
+        result = zext_bwid(result, bitwidth);
+    }
+    return sv_reg_t(result, xlen, bitwidth);
 }
 
 sv_sreg_t sv_proc_t::rv_mulhsu(sv_sreg_t const & lhs, sv_reg_t const & rhs)