From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 5 Aug 2007 03:17:31 +0000 (-0700)
Subject: X86: Make fixed register operands ignore register index extensions from the REX prefix.
X-Git-Tag: m5_2.0_beta4~199
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc6b2cceb4c16b8b33390b779d1ed64c84b1e954;p=gem5.git

X86: Make fixed register operands ignore register index extensions from the REX prefix.
The only cases where this was the correct behavior are now handled with the
"B" operand type, and doing things this way was breaking some instructions,
notably a shift.

--HG--
extra : convert_revision : 072346d4f541edaceba7aecc26ba8d2cd756e481
---

diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index b5f51ab58..690061de7 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -138,9 +138,9 @@ let {{
                 #Figure out what to do with fixed register operands
                 #This is the index to use, so we should stick it some place.
                 if opType.reg in ("A", "B", "C", "D"):
-                    env.addReg("INTREG_R%sX | (REX_B << 3)" % opType.reg)
+                    env.addReg("INTREG_R%sX" % opType.reg)
                 else:
-                    env.addReg("INTREG_R%s | (REX_B << 3)" % opType.reg)
+                    env.addReg("INTREG_R%s" % opType.reg)
                 Name += "_R"
             elif opType.tag == "B":
                 # This refers to registers whose index is encoded as part of the opcode