From: Ronald Dreslinski <rdreslin@umich.edu>
Date: Thu, 26 Jan 2012 19:53:48 +0000 (-0500)
Subject: configs: A more realistic configuration of an ARM-like processor
X-Git-Tag: stable_2012_06_28~266^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc7cf40de672fdae5272cb7b69123a44ae274ed6;p=gem5.git

configs: A more realistic configuration of an ARM-like processor
---

diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py
index 00517dfc4..364b20f28 100644
--- a/configs/common/CacheConfig.py
+++ b/configs/common/CacheConfig.py
@@ -32,11 +32,17 @@
 import m5
 from m5.objects import *
 from Caches import *
+from O3_ARM_v7a import *
 
 def config_cache(options, system):
     if options.l2cache:
-        system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
-                            block_size=options.cacheline_size)
+        if options.cpu_type == "arm_detailed":
+            system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc = options.l2_assoc,
+                                block_size=options.cacheline_size)
+        else:
+            system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
+                                block_size=options.cacheline_size)
+
         system.tol2bus = Bus()
         system.l2.cpu_side = system.tol2bus.port
         system.l2.mem_side = system.membus.port
@@ -44,10 +50,21 @@ def config_cache(options, system):
 
     for i in xrange(options.num_cpus):
         if options.caches:
-            icache = L1Cache(size = options.l1i_size, assoc = options.l1i_assoc,
-                             block_size=options.cacheline_size)
-            dcache = L1Cache(size = options.l1d_size, assoc = options.l1d_assoc,
-                             block_size=options.cacheline_size)
+            if options.cpu_type == "arm_detailed":
+                icache = O3_ARM_v7a_ICache(size = options.l1i_size,
+                                     assoc = options.l1i_assoc,
+                                     block_size=options.cacheline_size)
+                dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
+                                     assoc = options.l1d_assoc,
+                                     block_size=options.cacheline_size)
+            else:
+                icache = L1Cache(size = options.l1i_size,
+                                 assoc = options.l1i_assoc,
+                                 block_size=options.cacheline_size)
+                dcache = L1Cache(size = options.l1d_size,
+                                 assoc = options.l1d_assoc,
+                                 block_size=options.cacheline_size)
+
             if buildEnv['TARGET_ISA'] == 'x86':
                 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
                                                       PageTableWalkerCache(),
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 1941875bc..0932f2629 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -28,7 +28,8 @@
 
 # system options
 parser.add_option("--cpu-type", type="choice", default="atomic",
-                  choices = ["atomic", "timing", "detailed", "inorder"],
+                  choices = ["atomic", "timing", "detailed", "inorder",
+                             "arm_detailed"],
                   help = "type of cpu to run with")
 parser.add_option("-n", "--num-cpus", type="int", default=1)
 parser.add_option("--caches", action="store_true")
diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py
index 07cc323f9..193f8d487 100644
--- a/configs/common/Simulation.py
+++ b/configs/common/Simulation.py
@@ -34,6 +34,7 @@ import m5
 from m5.defines import buildEnv
 from m5.objects import *
 from m5.util import *
+from O3_ARM_v7a import *
 
 addToPath('../common')
 
@@ -42,11 +43,14 @@ def setCPUClass(options):
     atomic = False
     if options.cpu_type == "timing":
         class TmpClass(TimingSimpleCPU): pass
-    elif options.cpu_type == "detailed":
+    elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed":
         if not options.caches and not options.ruby:
             print "O3 CPU must be used with caches"
             sys.exit(1)
-        class TmpClass(DerivO3CPU): pass
+        if options.cpu_type == "arm_detailed":
+            class TmpClass(O3_ARM_v7a_3): pass
+        else:
+            class TmpClass(DerivO3CPU): pass
     elif options.cpu_type == "inorder":
         if not options.caches:
             print "InOrder CPU must be used with caches"