From: whitequark <cz@m-labs.hk>
Date: Sun, 16 Dec 2018 23:52:47 +0000 (+0000)
Subject: back.rtlil: handle reset_less domains.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fc8a345f01d4a6e790cbd1a7d2a033adcafc545a;p=nmigen.git

back.rtlil: handle reset_less domains.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 1836d75..67ffdd3 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -515,7 +515,8 @@ def convert_fragment(builder, fragment, name, top):
         for domain, _ in fragment.iter_sync():
             cd = fragment.domains[domain]
             compiler_state.resolve_curr(cd.clk)
-            compiler_state.resolve_curr(cd.rst)
+            if cd.rst is not None:
+                compiler_state.resolve_curr(cd.rst)
 
         # Transform all subfragments to their respective cells. Transforming signals connected
         # to their ports into wires eagerly makes sure they get sensible (prefixed with submodule