From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Aug 2019 07:10:28 +0000 (+0100)
Subject: do not make mul1 processing conditional on out_do_z
X-Git-Tag: ls180-24jan2020~395
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fca308545ce54b1b981c80e733706d37c42d7248;p=ieee754fpu.git

do not make mul1 processing conditional on out_do_z
---

diff --git a/src/ieee754/fpmul/mul1.py b/src/ieee754/fpmul/mul1.py
index ce73ab29..ea96a8b3 100644
--- a/src/ieee754/fpmul/mul1.py
+++ b/src/ieee754/fpmul/mul1.py
@@ -30,29 +30,28 @@ class FPMulStage1Mod(PipeModBase):
         comb = m.d.comb
 
         comb += self.o.z.eq(self.i.z)
-        with m.If(~self.i.out_do_z):
-            # results are in the range 0.25 to 0.999999999999
-            # sometimes the MSB will be zero, (0.5 * 0.5 = 0.25 which
-            # in binary is 0b010000) so to compensate for that we have
-            # to shift the mantissa up (and reduce the exponent by 1)
-            p = Signal(len(self.i.product), reset_less=True)
-            with m.If(self.i.product[-1]):
-                comb += p.eq(self.i.product)
-            with m.Else():
-                # get 1 bit of extra accuracy if the mantissa top bit is zero
-                comb += p.eq(self.i.product<<1)
-                comb += self.o.z.e.eq(self.i.z.e-1)
-
-            # top bits are mantissa, then guard and round, and the rest of
-            # the product is sticky
-            mw = self.o.z.m_width
-            comb += [
-                self.o.z.m.eq(p[mw+2:]),            # mantissa
-                self.o.of.m0.eq(p[mw+2]),           # copy of LSB
-                self.o.of.guard.eq(p[mw+1]),        # guard
-                self.o.of.round_bit.eq(p[mw]),      # round
-                self.o.of.sticky.eq(p[0:mw].bool()) # sticky
-            ]
+        # results are in the range 0.25 to 0.999999999999
+        # sometimes the MSB will be zero, (0.5 * 0.5 = 0.25 which
+        # in binary is 0b010000) so to compensate for that we have
+        # to shift the mantissa up (and reduce the exponent by 1)
+        p = Signal(len(self.i.product), reset_less=True)
+        with m.If(self.i.product[-1]):
+            comb += p.eq(self.i.product)
+        with m.Else():
+            # get 1 bit of extra accuracy if the mantissa top bit is zero
+            comb += p.eq(self.i.product<<1)
+            comb += self.o.z.e.eq(self.i.z.e-1)
+
+        # top bits are mantissa, then guard and round, and the rest of
+        # the product is sticky
+        mw = self.o.z.m_width
+        comb += [
+            self.o.z.m.eq(p[mw+2:]),            # mantissa
+            self.o.of.m0.eq(p[mw+2]),           # copy of LSB
+            self.o.of.guard.eq(p[mw+1]),        # guard
+            self.o.of.round_bit.eq(p[mw]),      # round
+            self.o.of.sticky.eq(p[0:mw].bool()) # sticky
+        ]
 
         comb += self.o.out_do_z.eq(self.i.out_do_z)
         comb += self.o.oz.eq(self.i.oz)