From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 11 Feb 2015 20:51:25 +0000 (+0100)
Subject: etherbone: wishbone reads seems OK in simulation
X-Git-Tag: 24jan2021_ls180~2604^2~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fca89e8b740e7ee64016957283d93f097a9f4d83;p=litex.git

etherbone: wishbone reads seems OK in simulation
---

diff --git a/liteeth/core/etherbone/record.py b/liteeth/core/etherbone/record.py
index 6c3acb0e..15abe58d 100644
--- a/liteeth/core/etherbone/record.py
+++ b/liteeth/core/etherbone/record.py
@@ -124,8 +124,11 @@ class LiteEthEtherboneRecordSender(Module):
 			source.sop.eq(0),
 			source.eop.eq(wr_buffer.source.eop),
 			source.data.eq(wr_buffer.source.data),
-			If(source.stb & source.eop & source.ack,
-				NextState("IDLE")
+			If(source.stb & source.ack,
+				wr_buffer.source.ack.eq(1),
+				If(source.eop,
+					NextState("IDLE")
+				)
 			)
 		)
 
@@ -143,10 +146,26 @@ class LiteEthEtherboneRecord(Module):
 			receiver.sink.data.eq(reverse_bytes(depacketizer.source.data)) # clarify this
 		]
 
+		last_ip_address = Signal(32) # XXX for test
+		last_src_port = Signal(16)   # XXX for test
+		last_dst_port = Signal(16)   # XXX for test
+
+		self.sync += [
+			If(sink.stb & sink.sop & sink.ack,
+				last_ip_address.eq(sink.ip_address),
+				last_src_port.eq(sink.src_port),
+				last_dst_port.eq(sink.dst_port)
+			)
+		]
+
 		self.submodules.sender = sender =  LiteEthEtherboneRecordSender()
 		self.submodules.packetizer = packetizer = LiteEthEtherboneRecordPacketizer()
 		self.comb += [
 			Record.connect(sender.source, packetizer.sink),
 			packetizer.sink.data.eq(reverse_bytes(sender.source.data)), # clarify this
 			Record.connect(packetizer.source, source),
+			source.length.eq(sender.source.wcount*4 + 4),
+			source.ip_address.eq(last_ip_address),
+			source.src_port.eq(last_src_port),
+			source.dst_port.eq(last_dst_port)
 		]
diff --git a/liteeth/core/etherbone/wishbone.py b/liteeth/core/etherbone/wishbone.py
index 50cd175d..fd58094d 100644
--- a/liteeth/core/etherbone/wishbone.py
+++ b/liteeth/core/etherbone/wishbone.py
@@ -58,7 +58,8 @@ class LiteEthEtherboneWishboneMaster(Module):
 			wr_source.addr.eq(rd_sink.addr),
 			wr_source.count.eq(rd_sink.count),
 			wr_source.be.eq(rd_sink.be),
-			wr_source.data.eq(data.q),
+			#wr_source.data.eq(data.q),
+			wr_source.data.eq(0x12345678), # XXX
 			If(wr_source.stb & wr_source.ack,
 				rd_sink.ack.eq(1),
 				If(wr_source.eop,
diff --git a/liteeth/test/etherbone_tb.py b/liteeth/test/etherbone_tb.py
index 1987e29a..5f32ae2d 100644
--- a/liteeth/test/etherbone_tb.py
+++ b/liteeth/test/etherbone_tb.py
@@ -50,35 +50,70 @@ class TB(Module):
 		for i in range(100):
 			yield
 
-		# test probe
-		#packet = etherbone.EtherbonePacket()
-		#packet.pf = 1
-		#self.etherbone_model.send(packet)
+		test_probe = False
+		test_writes = False
+		test_reads = True
 
-		# test writes
-		writes = etherbone.EtherboneWrites(base_addr=0x1000)
-		for i in range(16):
-			writes.add(etherbone.EtherboneWrite(i))
-		record = etherbone.EtherboneRecord()
-		record.writes = writes
-		record.reads = None
-		record.bca = 0
-		record.rca = 0
-		record.rff = 0
-		record.cyc = 0
-		record.wca = 0
-		record.wff = 0
-		record.byte_enable = 0
-		record.wcount = 16
-		record.rcount = 0
-
-		packet = etherbone.EtherbonePacket()
-		packet.records = [record]
-		print(packet)
-
-		self.etherbone_model.send(packet)
+		# test probe
+		if test_probe:
+			packet = etherbone.EtherbonePacket()
+			packet.pf = 1
+			self.etherbone_model.send(packet)
 
+			for i in range(1024):
+				yield
 
+		# test writes
+		if test_writes:
+			writes = etherbone.EtherboneWrites(base_addr=0x1000)
+			for i in range(16):
+				writes.add(etherbone.EtherboneWrite(i))
+			record = etherbone.EtherboneRecord()
+			record.writes = writes
+			record.reads = None
+			record.bca = 0
+			record.rca = 0
+			record.rff = 0
+			record.cyc = 0
+			record.wca = 0
+			record.wff = 0
+			record.byte_enable = 0
+			record.wcount = 16
+			record.rcount = 0
+
+			packet = etherbone.EtherbonePacket()
+			packet.records = [record]
+			print(packet)
+			self.etherbone_model.send(packet)
+
+			for i in range(1024):
+				yield
+
+		# test reads
+		if test_reads:
+			reads = etherbone.EtherboneReads(base_ret_addr=0x2000)
+			for i in range(16):
+				reads.add(etherbone.EtherboneRead(i))
+			record = etherbone.EtherboneRecord()
+			record.writes = None
+			record.reads = reads
+			record.bca = 0
+			record.rca = 0
+			record.rff = 0
+			record.cyc = 0
+			record.wca = 0
+			record.wff = 0
+			record.byte_enable = 0
+			record.wcount = 0
+			record.rcount = 16
+
+			packet = etherbone.EtherbonePacket()
+			packet.records = [record]
+			print(packet)
+			self.etherbone_model.send(packet)
+
+			for i in range(1024):
+				yield
 
 if __name__ == "__main__":
-	run_simulation(TB(), ncycles=1024, vcd_name="my.vcd", keep_files=True)
\ No newline at end of file
+	run_simulation(TB(), ncycles=4096, vcd_name="my.vcd", keep_files=True)
\ No newline at end of file
diff --git a/liteeth/test/model/etherbone.py b/liteeth/test/model/etherbone.py
index b4b3626f..5b1c0b8e 100644
--- a/liteeth/test/model/etherbone.py
+++ b/liteeth/test/model/etherbone.py
@@ -143,9 +143,11 @@ class EtherboneRecord(Packet):
 		for k, v in sorted(etherbone_record_header.items()):
 			setattr(self, k, get_field_data(v, header))
 		self.writes = self.get_writes()
-		self.writes.decode()
+		if self.writes is not None:
+			self.writes.decode()
 		self.reads = self.get_reads()
-		self.reads.decode()
+		if self.reads is not None:
+			self.reads.decode()
 		self.encoded = False
 
 	def set_writes(self, writes):