From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 25 Feb 2009 18:17:38 +0000 (-0800)
Subject: X86: Add a wrattr microop.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fcad6e3b13410ab6c7263ce42b5e657c16f79e1d;p=gem5.git

X86: Add a wrattr microop.
---

diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index f21621e30..4434f9e74 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1009,6 +1009,11 @@ let {{
             SegSelDest = psrc1;
         '''
 
+    class WrAttr(SegOp):
+        code = '''
+            SegAttrDest = psrc1;
+        '''
+
     class Rdbase(SegOp):
         code = '''
             DestReg = SegBaseSrc1;