From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 5 Apr 2017 09:25:22 +0000 (+0200)
Subject: Add ConstEval defaultval feature
X-Git-Tag: yosys-0.8~450
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fcb274a5644016c4090cdfbfbd795f311a7e58f5;p=yosys.git

Add ConstEval defaultval feature
---

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 4d48b45ea..0229f5045 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -36,8 +36,9 @@ struct ConstEval
 	SigSet<RTLIL::Cell*> sig2driver;
 	std::set<RTLIL::Cell*> busy;
 	std::vector<SigMap> stack;
+	RTLIL::State defaultval;
 
-	ConstEval(RTLIL::Module *module) : module(module), assign_map(module)
+	ConstEval(RTLIL::Module *module, RTLIL::State defaultval = RTLIL::State::Sm) : module(module), assign_map(module), defaultval(defaultval)
 	{
 		CellTypes ct;
 		ct.setup_internals();
@@ -365,6 +366,12 @@ struct ConstEval
 		if (sig.is_fully_const())
 			return true;
 
+		if (defaultval != RTLIL::State::Sm) {
+			for (auto &bit : sig)
+				if (bit.wire) bit = defaultval;
+			return true;
+		}
+
 		for (auto &c : sig.chunks())
 			if (c.wire != NULL)
 				undef.append(c);