From: Luke Kenneth Casson Leighton Date: Mon, 19 Sep 2022 22:51:38 +0000 (+0100) Subject: clarify vertical-first on REMAP X-Git-Tag: opf_rfc_ls005_v1~355 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fcc3936c41429d8073f0de39af93f436c6545b37;p=libreriscv.git clarify vertical-first on REMAP --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index b694ee4f3..74b83766a 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -530,7 +530,11 @@ temporary registers to compute results that have a Vector source or destination or both. Contrast this with a Standard Horizontal-First Vector ISA where the only way to perform Vectorised Complex Arithmetic would be to add Complex Vector -Arithmetic operations. +Arithmetic operations, because due to the Horizontal (element-level) +progression there is no way to utilise intermediary temporary (scalar) +variables.[^complex] + +[^complex]: a case could be made for constructing Complex number arithmetic using multiple sequential Horizontal-First (Cray-style Vector) instructions. This may not be convenient in the least when REMAP is involved (such as Parallel Reduction of Complex Multiply). * **DCT/FFT** REMAP brings more capability than TI's MSP-Series DSPs and Qualcom Hexagon DSPs, and is not restricted to Integer or FP.