From: whitequark <whitequark@whitequark.org>
Date: Thu, 13 Dec 2018 04:36:02 +0000 (+0000)
Subject: write_verilog: add a missing newline.
X-Git-Tag: yosys-0.9~371^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fccaa25ec1b053259a377991d8deba0f71021956;p=yosys.git

write_verilog: add a missing newline.
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index dde03f920..850abfad7 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1419,7 +1419,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
 				"can't always be mapped directly to Verilog always blocks. Unintended\n"
 				"changes in simulation behavior are possible! Use \"proc\" to convert\n"
-				"processes to logic networks and registers.", log_id(module));
+				"processes to logic networks and registers.\n", log_id(module));
 
 	f << stringf("\n");
 	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)