From: Samuel Iglesias Gonsálvez Date: Fri, 10 Feb 2017 13:06:43 +0000 (+0100) Subject: i965/fs: fix 32-bit data type to int64 conversion on BSW/BXT X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fccbad73effc88011b2236e042ad749c8bc15abd;p=mesa.git i965/fs: fix 32-bit data type to int64 conversion on BSW/BXT The 32-bit to 64-bit conversions need to have the 32-bit data source elements aligned to 64-bit but only with doubles as destination type. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 Signed-off-by: Samuel Iglesias Gonsálvez Tested-by: Mark Janes Reviewed-by: Matt Turner --- diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 96473000649..a977ee42731 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -655,13 +655,6 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) case nir_op_f2d: case nir_op_i2d: case nir_op_u2d: - case nir_op_f2i64: - case nir_op_f2u64: - case nir_op_i2i64: - case nir_op_i2u64: - case nir_op_u2i64: - case nir_op_u2u64: - case nir_op_b2i64: /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions: * * "When source or destination is 64b (...), regioning in Align1 @@ -686,6 +679,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; } /* fallthrough */ + case nir_op_f2i64: + case nir_op_f2u64: + case nir_op_i2i64: + case nir_op_i2u64: + case nir_op_u2i64: + case nir_op_u2u64: + case nir_op_b2i64: case nir_op_d2f: case nir_op_d2i: case nir_op_d2u: