From: Wesley W. Terpstra <wesley@sifive.com>
Date: Sat, 4 Mar 2017 02:51:37 +0000 (-0800)
Subject: sim: define emulated CPU clock rate to be 1GHz
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fcd0f3ab3b07b84ac2b3e62cf3534daff0fc0363;p=riscv-isa-sim.git

sim: define emulated CPU clock rate to be 1GHz
---

diff --git a/riscv/sim.h b/riscv/sim.h
index 5d165c9..f655914 100644
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -48,6 +48,7 @@ private:
   void step(size_t n); // step through simulation
   static const size_t INTERLEAVE = 5000;
   static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core
+  static const size_t CPU_HZ = 1000000000; // 1GHz CPU
   size_t current_step;
   size_t current_proc;
   bool debug;