From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Thu, 25 Jul 2013 15:56:55 +0000 (+0200)
Subject: examples/two_dividers: demonstrate InsertCE and InsertReset decorators
X-Git-Tag: 24jan2021_ls180~2099^2~506
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fcd48dafec4eef222ab7e7ba0415406c2bb0ab7e;p=litex.git

examples/two_dividers: demonstrate InsertCE and InsertReset decorators
---

diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
index 98759419..72352204 100644
--- a/examples/basic/two_dividers.py
+++ b/examples/basic/two_dividers.py
@@ -2,14 +2,16 @@ from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib import divider
 
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
 class Example(Module):
-	def __init__(self):
-		d1 = divider.Divider(16)
-		d2 = divider.Divider(16)
+	def __init__(self, width):
+		d1 = divider.Divider(width)
+		d2 = divider.Divider(width)
 		self.submodules += d1, d2
 		self.ios = {
 			d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
 			d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}
 
-example = Example()
-print(verilog.convert(example, example.ios))
+example = Example(16)
+print(verilog.convert(example, example.ios | {example.ce, example.reset}))