From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Wed, 17 Aug 2022 20:55:31 +0000 (+0300)
Subject: pysvp64dis: provide BC mode sketch
X-Git-Tag: sv_maxu_works-initial~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fcd526a71f10ae16dd19bcfc5788c65d23104e50;p=openpower-isa.git

pysvp64dis: provide BC mode sketch
---

diff --git a/src/openpower/sv/trans/pysvp64dis.py b/src/openpower/sv/trans/pysvp64dis.py
index 72b12841..fa3b8f34 100644
--- a/src/openpower/sv/trans/pysvp64dis.py
+++ b/src/openpower/sv/trans/pysvp64dis.py
@@ -3,9 +3,17 @@ import enum as _enum
 import functools as _functools
 import sys as _sys
 
-from openpower.decoder.power_enums import find_wiki_dir as _find_wiki_dir
+from openpower.decoder.power_enums import (
+    Function as _Function,
+    SVP64BCCTRMode as _SVP64BCCTRMode,
+    SVP64BCVLSETMode as _SVP64BCVLSETMode,
+    find_wiki_dir as _find_wiki_dir,
+)
 from openpower.decoder.power_insn import Database as _Database
-from openpower.decoder.selectable_int import SelectableInt as _SelectableInt
+from openpower.decoder.selectable_int import (
+    SelectableInt as _SelectableInt,
+)
+from openpower.consts import SVP64MODE as _SVP64MODE
 from openpower.decoder.isa.caller import (
     SVP64PrefixFields as _SVP64PrefixFields,
     SVP64RMFields as _SVP64RMFields,
@@ -118,6 +126,25 @@ class SVP64Instruction(PrefixedInstruction):
             yield f".llong 0x{self.value:08x}"
         else:
             yield f".llong 0x{self.value:08x} # sv.{self.dbrecord.name}"
+            rm = self.prefix.rm
+            mode = self.prefix.rm.mode
+            if self.dbrecord.function is _Function.BRANCH:
+                bc_ctrtest = _SVP64BCCTRMode.NONE
+                if mode[_SVP64MODE.BC_CTRTEST]:
+                    if rm.ewsrc[0]:
+                        bc_ctrtest = _SVP64BCCTRMode.TEST_INV
+                    else:
+                        bc_ctrtest = _SVP64BCCTRMode.TEST
+                bc_vlset = _SVP64BCVLSETMode.NONE
+                if mode[_SVP64MODE.BC_VLSET]:
+                    if mode[_SVP64MODE.BC_VLI]:
+                        bc_vlset = _SVP64BCVLSETMode.VL_INCL
+                    else:
+                        bc_vlset = _SVP64BCVLSETMode.VL_EXCL
+                bc_gate = rm.elwidth[0]
+                bc_lru = rm.elwidth[1]
+                bc_vsb = rm.ewsrc[1]
+
 
     @property
     def prefix(self):