From: Jacob Lifshay Date: Sat, 3 Sep 2022 01:44:08 +0000 (-0700) Subject: format code X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fcd58779df27e51b57991e9bf511cda2394dcf05;p=openpower-isa.git format code --- diff --git a/src/openpower/decoder/isa/test_caller_svshape2.py b/src/openpower/decoder/isa/test_caller_svshape2.py index fdef4ede..5a4ad091 100644 --- a/src/openpower/decoder/isa/test_caller_svshape2.py +++ b/src/openpower/decoder/isa/test_caller_svshape2.py @@ -22,19 +22,19 @@ from copy import deepcopy class SVSTATETestCase(FHDLTestCase): def _check_regs(self, sim, expected): - print ("GPR") + print("GPR") sim.gpr.dump() for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64), - "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i])) + "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i])) def test_0_sv_shape2(self): """sets VL=10 (via SVSTATE) then does svshape mm=0, checks SPRs after """ isa = SVP64Asm(['svshape2 12, 1, 15, 5, 0, 0' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -45,9 +45,9 @@ class SVSTATETestCase(FHDLTestCase): # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 10 # VL - svstate.maxvl = 10 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 10 # VL + svstate.maxvl = 10 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -57,35 +57,35 @@ class SVSTATETestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs, svstate=svstate) self._check_regs(sim, expected_regs) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0 ", SVSHAPE0) - print ("STATE0 offs", SVSHAPE0.offset) - print ("STATE0 xdim", SVSHAPE0.xdimsz) - print ("STATE0 ydim", SVSHAPE0.ydimsz) - print ("STATE0 skip", bin(SVSHAPE0.skip)) - print ("STATE0 inv", SVSHAPE0.invxyz) - print ("STATE0order", SVSHAPE0.order) - self.assertEqual(SVSHAPE0.xdimsz, 5) # set - self.assertEqual(SVSHAPE0.ydimsz, 2) # calculated from MVL/xdimsz + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0 ", SVSHAPE0) + print("STATE0 offs", SVSHAPE0.offset) + print("STATE0 xdim", SVSHAPE0.xdimsz) + print("STATE0 ydim", SVSHAPE0.ydimsz) + print("STATE0 skip", bin(SVSHAPE0.skip)) + print("STATE0 inv", SVSHAPE0.invxyz) + print("STATE0order", SVSHAPE0.order) + self.assertEqual(SVSHAPE0.xdimsz, 5) # set + self.assertEqual(SVSHAPE0.ydimsz, 2) # calculated from MVL/xdimsz self.assertEqual(SVSHAPE0.skip, 0) # no skip - self.assertEqual(SVSHAPE0.invxyz, 0) # (no inversion possible) + self.assertEqual(SVSHAPE0.invxyz, 0) # (no inversion possible) self.assertEqual(SVSHAPE0.offset, 12) - self.assertEqual(SVSHAPE0.order, (1, 0, 2)) # y,x(,z) - self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 - self.assertEqual(sim.svstate.SVme, 0b01111) # same as rmm + self.assertEqual(SVSHAPE0.order, (1, 0, 2)) # y,x(,z) + self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 + self.assertEqual(sim.svstate.SVme, 0b01111) # same as rmm # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0 self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 1) @@ -99,9 +99,9 @@ class SVSTATETestCase(FHDLTestCase): # rmm: bits 0-2 (MSB0) are 0b011 and bits 3-4 are 0b10. # therefore rmm is 0b011 || 0b10 --> 0b01110 -> 14 isa = SVP64Asm(['svindex 1, 14, 5, 0, 0, 1, 0' - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 @@ -112,9 +112,9 @@ class SVSTATETestCase(FHDLTestCase): # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 10 # VL - svstate.maxvl = 10 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 10 # VL + svstate.maxvl = 10 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -124,27 +124,27 @@ class SVSTATETestCase(FHDLTestCase): sim = self.run_tst_program(program, initial_regs, svstate=svstate) self._check_regs(sim, expected_regs) - print (sim.spr) + print(sim.spr) SVSHAPE2 = sim.spr['SVSHAPE2'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE2svgpr", hex(SVSHAPE2.svgpr)) - print ("STATE2 xdim", SVSHAPE2.xdimsz) - print ("STATE2 ydim", SVSHAPE2.ydimsz) - print ("STATE2 skip", bin(SVSHAPE2.skip)) - print ("STATE2 inv", SVSHAPE2.invxyz) - print ("STATE2order", SVSHAPE2.order) - self.assertEqual(sim.svstate.RMpst, 1) # mm=1 so persist=1 + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE2svgpr", hex(SVSHAPE2.svgpr)) + print("STATE2 xdim", SVSHAPE2.xdimsz) + print("STATE2 ydim", SVSHAPE2.ydimsz) + print("STATE2 skip", bin(SVSHAPE2.skip)) + print("STATE2 inv", SVSHAPE2.invxyz) + print("STATE2order", SVSHAPE2.order) + self.assertEqual(sim.svstate.RMpst, 1) # mm=1 so persist=1 # rmm is 0b01110 which means mo0 = 2 self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) @@ -154,13 +154,13 @@ class SVSTATETestCase(FHDLTestCase): # and mo0 should be activated self.assertEqual(sim.svstate.SVme, 0b01000) # now check the SVSHAPEs. 2 was the one targetted - self.assertEqual(SVSHAPE2.svgpr, 2) # SVG is shifted up by 1 + self.assertEqual(SVSHAPE2.svgpr, 2) # SVG is shifted up by 1 self.assertEqual(SVSHAPE2.xdimsz, 5) # SHAPE2 xdim set to 5 self.assertEqual(SVSHAPE2.ydimsz, 1) # SHAPE2 ydim 1 # all others must be zero - for i in [0,1,3]: + for i in [0, 1, 3]: shape = sim.spr['SVSHAPE%d' % i] - self.assertEqual(shape.asint(), 0) # all others zero + self.assertEqual(shape.asint(), 0) # all others zero def tst_0_sv_index_add(self): """sets VL=6 (via SVSTATE) then does svindex, and an add. @@ -169,22 +169,22 @@ class SVSTATETestCase(FHDLTestCase): """ isa = SVP64Asm(['svindex 8, 1, 1, 0, 0, 0, 0', 'sv.add *8, *0, *0', - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 - idxs = [1, 0, 5, 2, 4, 3] # random enough + idxs = [1, 0, 5, 2, 4, 3] # random enough for i in range(6): initial_regs[16+i] = idxs[i] initial_regs[i] = i # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 6 # VL - svstate.maxvl = 6 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 6 # VL + svstate.maxvl = 6 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -192,39 +192,39 @@ class SVSTATETestCase(FHDLTestCase): RA = initial_regs[0+idxs[i]] RB = initial_regs[0+i] expected_regs[i+8] = RA+RB - print ("expected", i, expected_regs[i+8]) + print("expected", i, expected_regs[i+8]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) - print (sim.gpr.dump()) - self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 - self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print(sim.gpr.dump()) + self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 + self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm # rmm is 0b00001 which means mi0=0 and all others inactive (0) self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) self.assertEqual(sim.svstate.mi2, 0) self.assertEqual(sim.svstate.mo0, 0) self.assertEqual(sim.svstate.mo1, 0) - self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 - for i in range(1,4): + self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 + for i in range(1, 4): shape = sim.spr['SVSHAPE%d' % i] - self.assertEqual(shape.svgpr, 0) + self.assertEqual(shape.svgpr, 0) self._check_regs(sim, expected_regs) def tst_1_sv_index_add(self): @@ -234,67 +234,67 @@ class SVSTATETestCase(FHDLTestCase): """ isa = SVP64Asm(['svindex 8, 1, 3, 0, 0, 0, 0', 'sv.add *8, *0, *0', - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 - idxs = [1, 0, 5, 2, 4, 3] # random enough + idxs = [1, 0, 5, 2, 4, 3] # random enough for i in range(6): initial_regs[16+i] = idxs[i] initial_regs[i] = i # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 6 # VL - svstate.maxvl = 6 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 6 # VL + svstate.maxvl = 6 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) for i in range(6): - RA = initial_regs[0+idxs[i%3]] # modulo 3 but still indexed + RA = initial_regs[0+idxs[i % 3]] # modulo 3 but still indexed RB = initial_regs[0+i] expected_regs[i+8] = RA+RB - print ("expected", i, expected_regs[i+8]) + print("expected", i, expected_regs[i+8]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) - print ("STATE0 xdim", SVSHAPE0.xdimsz) - print ("STATE0 ydim", SVSHAPE0.ydimsz) - print ("STATE0 skip", bin(SVSHAPE0.skip)) - print ("STATE0 inv", SVSHAPE0.invxyz) - print ("STATE0order", SVSHAPE0.order) - print (sim.gpr.dump()) - self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 - self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print("STATE0 xdim", SVSHAPE0.xdimsz) + print("STATE0 ydim", SVSHAPE0.ydimsz) + print("STATE0 skip", bin(SVSHAPE0.skip)) + print("STATE0 inv", SVSHAPE0.invxyz) + print("STATE0order", SVSHAPE0.order) + print(sim.gpr.dump()) + self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 + self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm # rmm is 0b00001 which means mi0=0 and all others inactive (0) self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) self.assertEqual(sim.svstate.mi2, 0) self.assertEqual(sim.svstate.mo0, 0) self.assertEqual(sim.svstate.mo1, 0) - self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 - for i in range(1,4): + self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 + for i in range(1, 4): shape = sim.spr['SVSHAPE%d' % i] - self.assertEqual(shape.svgpr, 0) + self.assertEqual(shape.svgpr, 0) self._check_regs(sim, expected_regs) def tst_2_sv_index_add(self): @@ -305,22 +305,22 @@ class SVSTATETestCase(FHDLTestCase): """ isa = SVP64Asm(['svindex 8, 1, 3, 0, 1, 0, 0', 'sv.add *8, *0, *0', - ]) + ]) lst = list(isa) - print ("listing", lst) + print("listing", lst) # initial values in GPR regfile initial_regs = [0] * 32 - idxs = [1, 0, 5, 2, 4, 3] # random enough + idxs = [1, 0, 5, 2, 4, 3] # random enough for i in range(6): initial_regs[16+i] = idxs[i] initial_regs[i] = i # SVSTATE vl=10 svstate = SVP64State() - svstate.vl = 6 # VL - svstate.maxvl = 6 # MAXVL - print ("SVSTATE", bin(svstate.asint())) + svstate.vl = 6 # VL + svstate.maxvl = 6 # MAXVL + print("SVSTATE", bin(svstate.asint())) # copy before running expected_regs = deepcopy(initial_regs) @@ -328,51 +328,51 @@ class SVSTATETestCase(FHDLTestCase): xi = i % 3 yi = i // 3 remap = yi+xi*2 - RA = initial_regs[0+idxs[remap]] # modulo 3 but still indexed + RA = initial_regs[0+idxs[remap]] # modulo 3 but still indexed RB = initial_regs[0+i] expected_regs[i+8] = RA+RB - print ("expected", i, expected_regs[i+8]) + print("expected", i, expected_regs[i+8]) with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) - print (sim.spr) + print(sim.spr) SVSHAPE0 = sim.spr['SVSHAPE0'] - print ("SVSTATE after", bin(sim.svstate.asint())) - print (" vl", bin(sim.svstate.vl)) - print (" mvl", bin(sim.svstate.maxvl)) - print (" srcstep", bin(sim.svstate.srcstep)) - print (" dststep", bin(sim.svstate.dststep)) - print (" RMpst", bin(sim.svstate.RMpst)) - print (" SVme", bin(sim.svstate.SVme)) - print (" mo0", bin(sim.svstate.mo0)) - print (" mo1", bin(sim.svstate.mo1)) - print (" mi0", bin(sim.svstate.mi0)) - print (" mi1", bin(sim.svstate.mi1)) - print (" mi2", bin(sim.svstate.mi2)) - print ("STATE0svgpr", hex(SVSHAPE0.svgpr)) - print ("STATE0 xdim", SVSHAPE0.xdimsz) - print ("STATE0 ydim", SVSHAPE0.ydimsz) - print ("STATE0 skip", bin(SVSHAPE0.skip)) - print ("STATE0 inv", SVSHAPE0.invxyz) - print ("STATE0order", SVSHAPE0.order) - print (sim.gpr.dump()) - self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 - self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm + print("SVSTATE after", bin(sim.svstate.asint())) + print(" vl", bin(sim.svstate.vl)) + print(" mvl", bin(sim.svstate.maxvl)) + print(" srcstep", bin(sim.svstate.srcstep)) + print(" dststep", bin(sim.svstate.dststep)) + print(" RMpst", bin(sim.svstate.RMpst)) + print(" SVme", bin(sim.svstate.SVme)) + print(" mo0", bin(sim.svstate.mo0)) + print(" mo1", bin(sim.svstate.mo1)) + print(" mi0", bin(sim.svstate.mi0)) + print(" mi1", bin(sim.svstate.mi1)) + print(" mi2", bin(sim.svstate.mi2)) + print("STATE0svgpr", hex(SVSHAPE0.svgpr)) + print("STATE0 xdim", SVSHAPE0.xdimsz) + print("STATE0 ydim", SVSHAPE0.ydimsz) + print("STATE0 skip", bin(SVSHAPE0.skip)) + print("STATE0 inv", SVSHAPE0.invxyz) + print("STATE0order", SVSHAPE0.order) + print(sim.gpr.dump()) + self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0 + self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm # rmm is 0b00001 which means mi0=0 and all others inactive (0) self.assertEqual(sim.svstate.mi0, 0) self.assertEqual(sim.svstate.mi1, 0) self.assertEqual(sim.svstate.mi2, 0) self.assertEqual(sim.svstate.mo0, 0) self.assertEqual(sim.svstate.mo1, 0) - self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 - for i in range(1,4): + self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1 + for i in range(1, 4): shape = sim.spr['SVSHAPE%d' % i] - self.assertEqual(shape.svgpr, 0) + self.assertEqual(shape.svgpr, 0) self._check_regs(sim, expected_regs) def run_tst_program(self, prog, initial_regs=None, - svstate=None): + svstate=None): if initial_regs is None: initial_regs = [0] * 32 simulator = run_tst(prog, initial_regs, svstate=svstate) @@ -382,4 +382,3 @@ class SVSTATETestCase(FHDLTestCase): if __name__ == "__main__": unittest.main() -