From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 12 Dec 2019 23:02:46 +0000 (-0800)
Subject: Remove 'clkpart' entry in CHANGELOG
X-Git-Tag: working-ls180~881^2^2~82
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fce6bad6ae22a3e14115202b05b50ae4a69b5a93;p=yosys.git

Remove 'clkpart' entry in CHANGELOG
---

diff --git a/CHANGELOG b/CHANGELOG
index d9d261fbc..a49c27b05 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -53,7 +53,6 @@ Yosys 0.9 .. Yosys 0.9-dev
     - Added "check -mapped"
     - Added checking of SystemVerilog always block types (always_comb,
       always_latch and always_ff)
-    - Added "clkpart" pass
 
 Yosys 0.8 .. Yosys 0.9
 ----------------------