From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 6 May 2021 16:26:52 +0000 (+0100)
Subject: add first SVP64 predicate dest-zeroing unit test
X-Git-Tag: 0.0.3~69
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fceb766a07dc1272d6a03fd024d07f44258084ef;p=openpower-isa.git

add first SVP64 predicate dest-zeroing unit test
---

diff --git a/src/openpower/test/logical/svp64_cases.py b/src/openpower/test/logical/svp64_cases.py
index 0c4591da..88c0de5b 100644
--- a/src/openpower/test/logical/svp64_cases.py
+++ b/src/openpower/test/logical/svp64_cases.py
@@ -360,3 +360,32 @@ class SVP64LogicalTestCase(TestAccumulatorBase):
 
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate, initial_cr=cr.cr.asint())
+
+    def case_sv_extsw_intpred_dz(self):
+        """>>> lst = ['sv.extsb/dm=r3/dz 5.v, 9.v']
+
+        extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest.
+        this test will put a zero into the element where its corresponding
+        predicate dest mask bit is also zero.
+        """
+        isa = SVP64Asm(['sv.extsb/dm=r3/dz 5.v, 9.v'
+                       ])
+        lst = list(isa)
+        print ("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[3] = 0b01   # predicate mask (dest)
+        initial_regs[5] = 0xfeed # going to be overwritten
+        initial_regs[6] = 0xbeef # going to be overwritten (with zero)
+        initial_regs[9] = 0x91   # dest r3 is 0b01 so this will be used
+        initial_regs[10] = 0x90  # this gets read but the output gets zero'd
+        # SVSTATE (in this case, VL=2)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
+        print ("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)
+