From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Tue, 21 Jul 2020 11:30:08 +0000 (+0200)
Subject: Replace Switch with If statement, indentation fixup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd24970fb918c623c8498ffdabb57dbaca7565d3;p=gram.git

Replace Switch with If statement, indentation fixup
---

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 88b6e8f..89bc244 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -282,8 +282,7 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
 
                                      # Writes (generate shifted ECLK clock for writes)
                                      o_DQSW270=dqsw270,
-                                     o_DQSW=dqsw
-                                     )
+                                     o_DQSW=dqsw)
             burstdet_d = Signal()
             m.d.sync += burstdet_d.eq(burstdet)
             with m.If(self._burstdet_clr.w_stb):
@@ -307,22 +306,22 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
                 dfi.phases[1].wrdata_mask[3*databits//8+i]),
             )
             m.d.sync += dm_o_data_d.eq(dm_o_data)
-            with m.Switch(bl8_chunk):
-                with m.Case(0):
-                    m.d.sync += dm_o_data_muxed.eq(dm_o_data[:4])
-                with m.Case(1):
-                    m.d.sync += dm_o_data_muxed.eq(dm_o_data_d[4:])
+
+            with m.If(bl8_chunk):
+                m.d.sync += dm_o_data_muxed.eq(dm_o_data_d[4:])
+            with m.Else():
+                m.d.sync += dm_o_data_muxed.eq(dm_o_data[:4])
+
             m.submodules += Instance("ODDRX2DQA",
-                                     i_RST=ResetSignal("dramsync"),
-                                     i_ECLK=ClockSignal("sync2x"),
-                                     i_SCLK=ClockSignal("dramsync"),
-                                     i_DQSW270=dqsw270,
-                                     i_D0=dm_o_data_muxed[0],
-                                     i_D1=dm_o_data_muxed[1],
-                                     i_D2=dm_o_data_muxed[2],
-                                     i_D3=dm_o_data_muxed[3],
-                                     o_Q=self.pads.dm.o[i]
-                                     )
+                i_RST=ResetSignal("dramsync"),
+                i_ECLK=ClockSignal("sync2x"),
+                i_SCLK=ClockSignal("dramsync"),
+                i_DQSW270=dqsw270,
+                i_D0=dm_o_data_muxed[0],
+                i_D1=dm_o_data_muxed[1],
+                i_D2=dm_o_data_muxed[2],
+                i_D3=dm_o_data_muxed[3],
+                o_Q=self.pads.dm.o[i])
 
             dqs = Signal()
             dqs_oe_n = Signal()