From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 4 Feb 2011 04:56:27 +0000 (-0800)
Subject: Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.
X-Git-Tag: stable_2012_02_02~619
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd2670773195378d2a91a47365ade97e917394f2;p=gem5.git

Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.
---

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 6568f4c89..1a052e282 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -153,7 +153,14 @@ if options.caches or options.l2cache:
         mem_size = bm[0].mem()
     else:
         mem_size = SysConfig().mem()
-    test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+    # For x86, we need to poke a hole for interrupt messages to get back to the
+    # CPU. These use a portion of the physical address space which has a
+    # non-zero prefix in the top nibble. Normal memory accesses have a 0
+    # prefix.
+    if buildEnv['TARGET_ISA'] == 'x86':
+        test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)]
+    else:
+        test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
     test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
     test_sys.iocache = IOCache(addr_range=mem_size)
     test_sys.iocache.cpu_side = test_sys.iobus.port