From: lkcl <lkcl@web>
Date: Sun, 4 Sep 2022 20:26:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~697
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd28eb9f1cd1b021e419bf120ae172a41f679522;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index bba461080..726db6904 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -101,12 +101,14 @@ Comparative Basic Design Principle:
   guaranteeing binary interoperability)
 * Intel AVX-512 (and below): Hybrid Packed-Predicated SIMD with no
   instruction-overloading, guaranteeing binary interoperability
-  but penalising the ISA with uncontrolled opcode proliferation.
+  but at the same time penalising the ISA with runaway
+  opcode proliferation.
 * ARM SVE/SVE2: Hybrid Packed-Predicated SIMD with instruction-overloading
   that destroys binary interoperability. This is hidden behind the
-  misuse of the word "Scalable".
+  misuse of the word "Scalable" and is **permitted under License**
+  by "Silicon Partners".
 * RISC-V RVV: Cray-style Scalable Vector but with instruction-overloading
-  that destroys binary interoperability.
+  **permitted by the specification** that destroys binary interoperability.
 * SVP64: Cray-style Scalable Vector with no instruction-overloaded
   meanings.  The regfile numbers and bitwidths shall **not** change
   in a future revision (for the same instruction encoding):