From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 24 Sep 2022 16:00:28 +0000 (+0100)
Subject: add assert to stop failfirst+sea
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd2f80aba3f04a81e42a3342c3c83c2ad5d93de5;p=openpower-isa.git

add assert to stop failfirst+sea
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 61438284..58cf4f1b 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1123,6 +1123,7 @@ class SVP64Asm:
                 assert sv_mode is None
                 sv_mode = 0b01
                 failfirst = decode_ffirst(encmode[3:])
+                assert sea is False, "cannot use failfirst with signed-address"
             # predicate-result, interestingly same as fail-first
             elif encmode.startswith("pr="):
                 assert sv_mode is None
@@ -1146,6 +1147,14 @@ class SVP64Asm:
             elif encmode == 'vli':
                 assert sv_mode == 0b01 # only allow ff mode
                 vli = True
+<<<<<<< HEAD
+=======
+            elif encmode == 'sea':
+                assert sv_mode in (None, 0b00, 0b01)
+                assert rm['mode'] == "LDST_IDX"
+                sea = True
+                assert failfirst is False, "cannot use ffirst+signed-address"
+>>>>>>> 54866195 (add asserts to ensure failfirst+sea not attempted)
             elif is_bc:
                 if encmode == 'all':
                     svp64_rm.branch.ALL = 1