From: Daniel R. Carvalho <odanrc@yahoo.com.br>
Date: Tue, 6 Oct 2020 10:56:09 +0000 (+0200)
Subject: mem-cache: Debug with blk's information instead of its state.
X-Git-Tag: develop-gem5-snapshot~671
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd3a17b916bd6aa4b63b68274c7518b3089e9d0d;p=gem5.git

mem-cache: Debug with blk's information instead of its state.

The print() function has been defined to facilitate debugging
regarding a block's metadata. Use it instead of accessing the
coherence bits directly.

Change-Id: Iba41f4ac067561970621a4bba809e1b315b0210d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35697
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 4b7333c1e..fc2115a2a 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1310,7 +1310,7 @@ BaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
     Addr addr = pkt->getAddr();
     bool is_secure = pkt->isSecure();
 #if TRACING_ON
-    CacheBlk::State old_state = blk ? blk->status : 0;
+    const std::string old_state = blk ? blk->print() : "";
 #endif
 
     // When handling a fill, we should have no writes to this line.
@@ -1380,7 +1380,7 @@ BaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
         }
     }
 
-    DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
+    DPRINTF(Cache, "Block addr %#llx (%s) moving from %s to %s\n",
             addr, is_secure ? "s" : "ns", old_state, blk->print());
 
     // if we got new data, copy it in (checking for a read response
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index a46404b69..8e45ea347 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -590,7 +590,7 @@ Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
             bus_pkt->print());
 
 #if TRACING_ON
-    CacheBlk::State old_state = blk ? blk->status : 0;
+    const std::string old_state = blk ? blk->print() : "";
 #endif
 
     Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt));
@@ -598,7 +598,7 @@ Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
     bool is_invalidate = bus_pkt->isInvalidate();
 
     // We are now dealing with the response handling
-    DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__,
+    DPRINTF(Cache, "%s: Receive response: %s for %s\n", __func__,
             bus_pkt->print(), old_state);
 
     // If packet was a forward, the response (if any) is already