From: Luke Kenneth Casson Leighton Date: Fri, 5 Apr 2019 18:22:37 +0000 (+0100) Subject: experimenting: something odd with dynamic ready/valid override X-Git-Tag: ls180-24jan2020~1335 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd3de4f12a062566e959b4122d39889cf37e28d9;p=ieee754fpu.git experimenting: something odd with dynamic ready/valid override --- diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py index 415f4b75..9f66de42 100644 --- a/src/add/singlepipe.py +++ b/src/add/singlepipe.py @@ -514,7 +514,7 @@ class ControlBase: res += self.n.o_data return res - def elaborate(self, platform): + def _elaborate(self, platform): """ handles case where stage has dynamic ready/valid functions """ m = Module() @@ -523,6 +523,10 @@ class ControlBase: # when the pipeline (buffered or otherwise) says "ready", # test the *stage* "ready". + m.d.comb += self.p.s_o_ready.eq(self.p._o_ready) + m.d.comb += self.n.s_o_valid.eq(self.n._o_valid) + return m + with m.If(self.p._o_ready): m.d.comb += self.p.s_o_ready.eq(self.stage.p_o_ready) with m.Else(): @@ -577,7 +581,7 @@ class BufferedPipeline(ControlBase): def elaborate(self, platform): - self.m = ControlBase.elaborate(self, platform) + self.m = ControlBase._elaborate(self, platform) result = self.stage.ospec() r_data = self.stage.ospec() @@ -675,7 +679,7 @@ class UnbufferedPipeline(ControlBase): self.n.o_data = stage.ospec() # output type def elaborate(self, platform): - self.m = ControlBase.elaborate(self, platform) + self.m = ControlBase._elaborate(self, platform) data_valid = Signal() # is data valid or not r_data = self.stage.ispec() # input type diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py index 192cc326..db0b364a 100644 --- a/src/add/test_buf_pipe.py +++ b/src/add/test_buf_pipe.py @@ -608,13 +608,13 @@ class ExampleStageDelayCls(StageCls): return i + 1 -class ExampleBufDelayedPipe(BufferedPipeline): +class ExampleBufDelayedPipe(UnbufferedPipeline): """ an example of how to use the buffered pipeline. """ def __init__(self): stage = ExampleStageDelayCls() - BufferedPipeline.__init__(self, stage, stage_ctl=True) + UnbufferedPipeline.__init__(self, stage, stage_ctl=False) class ExampleBufPipe3(ControlBase): @@ -623,7 +623,7 @@ class ExampleBufPipe3(ControlBase): """ def elaborate(self, platform): - m = Module() + m = ControlBase._elaborate(self, platform) pipe1 = ExampleBufPipe() pipe2 = ExampleBufDelayedPipe()