From: lkcl <lkcl@web>
Date: Wed, 2 Dec 2020 12:04:36 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1537
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd4165fdd8b82b15c2bfc7fc46763ce92f9c958d;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index e52300063..5650694e7 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -31,13 +31,15 @@ Note that setmvli is a pseudo-op, based on RA/RT=0, and setvli likewise
     // set VL (or not).
     // 3 options: from SPR, from immed, from ra
     if vs {
-       if ra == 0 {
-           VL = SPR[SV_VL]
+       // VL to be sourced from fields/regs
+       if ra != 0 {
+           VL = GPR[ra]  
        } else {
            VL = vlimmed
        }
-    } elif ra != 0 {
-       VL = GPR[ra]
+    } else {
+       // VL not to change, source from SPR
+       VL = SPR[SV_VL]
     }
 
     // set MVL (or not).