From: Daniel Benusovich Date: Wed, 6 Mar 2019 06:22:42 +0000 (-0800) Subject: Remove whitespace X-Git-Tag: div_pipeline~2341 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd42aa47e456ea80d12e287810b1d1c0cf0eca3f;p=soc.git Remove whitespace --- diff --git a/TLB/test/test_cam.py b/TLB/test/test_cam.py index 60445dfd..4bd1cfe9 100644 --- a/TLB/test/test_cam.py +++ b/TLB/test/test_cam.py @@ -40,7 +40,7 @@ def check_all(dut, multiple_match, single_match, match_address, mm_op, sm_op, ma yield from check_multiple_match(dut, multiple_match, mm_op) yield from check_single_match(dut, single_match, sm_op) yield from check_match_address(dut, match_address, ma_op) - + def testbench(dut): @@ -53,7 +53,7 @@ def testbench(dut): yield from set_cam(dut, enable, write_enable, address, data) yield yield from check_single_match(dut, single_match, 0) - + # Read Miss Multiple # Note that the default starting entry data bits are all 0 enable = 1 @@ -64,7 +64,7 @@ def testbench(dut): single_match = 0 yield from set_cam(dut, enable, write_enable, address, data) yield - yield from check_multiple_match(dut, multiple_match, 0) + yield from check_multiple_match(dut, multiple_match, 0) # Read Miss # Note that the default starting entry data bits are all 0