From: Florent Kermarrec Date: Sat, 16 Mar 2019 20:25:02 +0000 (+0100) Subject: utils/litex_sim: fix main_ram_size X-Git-Tag: 24jan2021_ls180~1359 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd7ed6c1ec24ffbdbebb465bc8cc4713b6d40181;p=litex.git utils/litex_sim: fix main_ram_size --- diff --git a/litex/utils/litex_sim.py b/litex/utils/litex_sim.py index 3a485a97..808bd8b9 100755 --- a/litex/utils/litex_sim.py +++ b/litex/utils/litex_sim.py @@ -224,7 +224,7 @@ def main(): if args.rom_init: soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness) if not args.with_sdram: - soc_kwargs["integrated_main_ram_size"] = 0x1000000 # 256 MB + soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB if args.ram_init is not None: soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness) else: