From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 9 Apr 2019 21:32:39 +0000 (-0700)
Subject: synth_xilinx to call abc with -lut +/xilinx/cells.lut
X-Git-Tag: working-ls180~1208^2~371
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd88ab5c834a45f4828a03fe7722b321e5f7c032;p=yosys.git

synth_xilinx to call abc with -lut +/xilinx/cells.lut
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index eb37feb83..e2a2dfeeb 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -276,9 +276,9 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
 			if (abc == "abc9")
-				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
+				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
 			else
-				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+				Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
 		}