From: Paul Mackerras Date: Thu, 27 Jul 2023 04:58:09 +0000 (+1000) Subject: Implement set[n]bc[r] instructions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fd8c0000c03c00be91aee83f578ccf18ccbcb5bb;p=microwatt.git Implement set[n]bc[r] instructions This implements the setbc, setnbc, setbcr and setnbcr instructions. Because the insn_type_t type already has 64 elements, this uses the existing OP_SETB for the new instructions, and has execute1 compute different results depending on bits 6-9 of the instruction. Signed-off-by: Paul Mackerras --- diff --git a/execute1.vhdl b/execute1.vhdl index e6cfd3e..e537048 100644 --- a/execute1.vhdl +++ b/execute1.vhdl @@ -836,14 +836,27 @@ begin end if; misc_result <= mfcr_result; when "110" => - -- setb - bfa := insn_bfa(e_in.insn); - crbit := to_integer(unsigned(bfa)) * 4; + -- setb and set[n]bc[r] setb_result := (others => '0'); - if cr_in(31 - crbit) = '1' then - setb_result := (others => '1'); - elsif cr_in(30 - crbit) = '1' then - setb_result(0) := '1'; + if e_in.insn(9) = '0' then + -- setb + bfa := insn_bfa(e_in.insn); + crbit := to_integer(unsigned(bfa)) * 4; + if cr_in(31 - crbit) = '1' then + setb_result := (others => '1'); + elsif cr_in(30 - crbit) = '1' then + setb_result(0) := '1'; + end if; + else + -- set[n]bc[r] + crbit := to_integer(unsigned(insn_bi(e_in.insn))); + if (cr_in(31 - crbit) xor e_in.insn(6)) = '1' then + if e_in.insn(7) = '0' then + setb_result(0) := '1'; + else + setb_result := (others => '1'); + end if; + end if; end if; misc_result <= setb_result; when others => diff --git a/predecode.vhdl b/predecode.vhdl index 41b26ad..58b17e3 100644 --- a/predecode.vhdl +++ b/predecode.vhdl @@ -336,6 +336,10 @@ architecture behaviour of predecoder is 2#0_00101_11010# => INSN_prtyd, 2#0_00100_11010# => INSN_prtyw, 2#0_00100_00000# => INSN_setb, + 2#0_01100_00000# => INSN_setb, -- setbc + 2#0_01101_00000# => INSN_setb, -- setbcr + 2#0_01110_00000# => INSN_setb, -- setnbc + 2#0_01111_00000# => INSN_setb, -- setnbcr 2#0_01111_10010# => INSN_slbia, 2#0_00000_11011# => INSN_sld, 2#0_00000_11000# => INSN_slw,