From: H.J. Lu <hongjiu.lu@intel.com>
Date: Sat, 20 Oct 2018 20:41:10 +0000 (+0000)
Subject: i386: Enable AVX512 memory broadcast for FP div
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fda5d5e6e040d23e7e751a491097090b8f5ff58a;p=gcc.git

i386: Enable AVX512 memory broadcast for FP div

Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for FP div operations.

gcc/

	PR target/72782
	* config/i386/sse.md (*<avx512>_div<mode>3<mask_name>_bcst): New.

gcc/testsuite/

	PR target/72782
	* gcc.target/i386/avx512f-div-df-zmm-1.c: New test.
	* gcc.target/i386/avx512f-div-sf-zmm-1.c: Likewise.
	* gcc.target/i386/avx512f-div-sf-zmm-2.c: Likewise.
	* gcc.target/i386/avx512f-div-sf-zmm-3.c: Likewise.
	* gcc.target/i386/avx512f-div-sf-zmm-4.c: Likewise.
	* gcc.target/i386/avx512f-div-sf-zmm-5.c: Likewise.
	* gcc.target/i386/avx512vl-div-sf-xmm-1.c: Likewise.
	* gcc.target/i386/avx512vl-div-sf-ymm-1.c: Likewise.

From-SVN: r265345
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f59167cca89..d5b092b526e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/72782
+	* config/i386/sse.md (*<avx512>_div<mode>3<mask_name>_bcst): New.
+
 2018-10-20  Jakub Jelinek  <jakub@redhat.com>
 
 	PR middle-end/87647
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 411c78ae8d3..1b41aa5088b 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1812,6 +1812,18 @@
    (set_attr "prefix" "<mask_prefix3>")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "*<avx512>_div<mode>3<mask_name>_bcst"
+  [(set (match_operand:VF_AVX512 0 "register_operand" "=v")
+	(div:VF_AVX512
+	  (match_operand:VF_AVX512 1 "register_operand" "v")
+	  (vec_duplicate:VF_AVX512
+	     (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
+  "TARGET_AVX512F && <mask_mode512bit_condition>"
+  "vdiv<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<<avx512bcst>>}"
+  [(set_attr "prefix" "evex")
+    (set_attr "type" "ssediv")
+   (set_attr "mode" "<MODE>")])
+
 (define_insn "<sse>_rcp<mode>2"
   [(set (match_operand:VF1_128_256 0 "register_operand" "=x")
 	(unspec:VF1_128_256
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index eff5d08faed..82a722ea949 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2018-10-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/72782
+	* gcc.target/i386/avx512f-div-df-zmm-1.c: New test.
+	* gcc.target/i386/avx512f-div-sf-zmm-1.c: Likewise.
+	* gcc.target/i386/avx512f-div-sf-zmm-2.c: Likewise.
+	* gcc.target/i386/avx512f-div-sf-zmm-3.c: Likewise.
+	* gcc.target/i386/avx512f-div-sf-zmm-4.c: Likewise.
+	* gcc.target/i386/avx512f-div-sf-zmm-5.c: Likewise.
+	* gcc.target/i386/avx512vl-div-sf-xmm-1.c: Likewise.
+	* gcc.target/i386/avx512vl-div-sf-ymm-1.c: Likewise.
+
 2018-10-20  Marek Polacek  <polacek@redhat.com>
 
 	* g++.dg/*.C: Use target c++17 instead of explicit dg-options.
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-div-df-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-div-df-zmm-1.c
new file mode 100644
index 00000000000..7c40112bbcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-div-df-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vdivpd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastsd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512d
+#define vec 512
+#define op div
+#define suffix pd
+#define SCALAR double
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-1.c
new file mode 100644
index 00000000000..b131929eeba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512
+#define vec 512
+#define op div
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-2.c
new file mode 100644
index 00000000000..373e3c63c03
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vdivps\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op div
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-3.c
new file mode 100644
index 00000000000..84e78198175
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vdivps\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op div
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-4.c
new file mode 100644
index 00000000000..44a34566a93
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op div
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-5.c
new file mode 100644
index 00000000000..81cf6b293d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-div-sf-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vbroadcastss\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vdivps\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512
+#define vec 512
+#define op div
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-6.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-div-sf-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-div-sf-xmm-1.c
new file mode 100644
index 00000000000..c7fb7a733ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-div-sf-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128
+#define vec
+#define op div
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-div-sf-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-div-sf-ymm-1.c
new file mode 100644
index 00000000000..536bc917abc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-div-sf-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vdivps\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vbroadcastss\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256
+#define vec 256
+#define op div
+#define suffix ps
+#define SCALAR float
+
+#include "avx512-binop-1.h"