From: Luke Kenneth Casson Leighton Date: Sun, 8 Apr 2018 14:48:45 +0000 (+0100) Subject: add mention of load/store in questions/analysis X-Git-Tag: convert-csv-opcode-to-binary~5716 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fda847001bddf9147faff4be780963e10b70cf75;p=libreriscv.git add mention of load/store in questions/analysis --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index d90723c11..b5497b2ea 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -811,6 +811,10 @@ greatly reduce CSR space: (See "CSR vector-length and CSR SIMD packed-bitwidth" section for details) +In addition, LOAD/STORE has its own associated proposed CSRs that +mirror the STRIDE (but not yet STRIDE-SEGMENT?) functionality of +V (and Hwacha). + Also bear in mind that, for reasons of simplicity for implementors, I was coming round to the idea of permitting implementors to choose exactly which bitwidths they would like to support in hardware and which