From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Mar 2020 18:15:17 +0000 (+0000)
Subject: destarify debug
X-Git-Tag: div_pipeline~1707
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fdac0e016f44044bb154bb4c764ed0ca909de727;p=soc.git

destarify debug
---

diff --git a/src/soc/minerva/units/debug/controller.py b/src/soc/minerva/units/debug/controller.py
index 31641baf..7304303e 100644
--- a/src/soc/minerva/units/debug/controller.py
+++ b/src/soc/minerva/units/debug/controller.py
@@ -1,8 +1,8 @@
-from nmigen import *
+from nmigen import Elaboratable, Module, Signal, Array, Record
 from nmigen.lib.coding import PriorityEncoder
 
-from ...csr import *
-from ...isa import *
+from ...csr import AutoCSR, CSR
+from ...isa import dcsr_layout, flat_layout
 from ...wishbone import wishbone_layout
 from .dmi import DebugReg, Command, Error, Version, cmd_access_reg_layout
 
diff --git a/src/soc/minerva/units/debug/jtag.py b/src/soc/minerva/units/debug/jtag.py
index e979789d..331dd512 100644
--- a/src/soc/minerva/units/debug/jtag.py
+++ b/src/soc/minerva/units/debug/jtag.py
@@ -1,4 +1,4 @@
-from nmigen.hdl.rec import *
+from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT
 
 
 __all__ = ["jtag_layout", "JTAGReg", "dtmcs_layout", "dmi_layout"]
diff --git a/src/soc/minerva/units/debug/regfile.py b/src/soc/minerva/units/debug/regfile.py
index a27e3bd1..a7d3fd4f 100644
--- a/src/soc/minerva/units/debug/regfile.py
+++ b/src/soc/minerva/units/debug/regfile.py
@@ -1,7 +1,8 @@
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Record, Const
 
-from .dmi import *
+from .dmi import (DebugReg, DmiOp, RegMode,
+                  abstractcs_layout, cmd_access_reg_layout, command_layout,
+                  dmcontrol_layout, dmstatus_layout, flat_layout, sbcs_layout)
 
 
 __all__ = ["DebugRegisterFile"]
diff --git a/src/soc/minerva/units/debug/top.py b/src/soc/minerva/units/debug/top.py
index e5cf4041..53b92ebe 100644
--- a/src/soc/minerva/units/debug/top.py
+++ b/src/soc/minerva/units/debug/top.py
@@ -1,16 +1,14 @@
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Signal, Record
 
 
-from ...csr import *
-from ...isa import *
+from ...csr import AutoCSR, CSR
 from ...wishbone import wishbone_layout
-from .controller import *
-from .dmi import *
-from .jtag import *
-from .regfile import *
-from .wbmaster import *
+from .controller import DebugController
+from .jtag import JTAGReg, dtmcs_layout, dmi_layout, jtag_layout
+from .regfile import DebugRegisterFile
+from .wbmaster import wishbone_layout, DebugWishboneMaster
 
+from jtagtap import JTAGTap
 
 __all__ = ["DebugUnit"]
 
@@ -69,7 +67,6 @@ class DebugUnit(Elaboratable, AutoCSR):
     def elaborate(self, platform):
         m = Module()
 
-        from jtagtap import JTAGTap
         tap        = m.submodules.tap        = JTAGTap(jtag_regs)
         regfile    = m.submodules.regfile    = DebugRegisterFile(tap.regs[JTAGReg.DMI])
         controller = m.submodules.controller = DebugController(regfile)
diff --git a/src/soc/minerva/units/debug/wbmaster.py b/src/soc/minerva/units/debug/wbmaster.py
index a4711568..db02af95 100644
--- a/src/soc/minerva/units/debug/wbmaster.py
+++ b/src/soc/minerva/units/debug/wbmaster.py
@@ -1,11 +1,10 @@
 from functools import reduce
 from operator import or_
 
-from nmigen import *
-from nmigen.hdl.rec import *
+from nmigen import Elaboratable, Module, Signal, Record
 
 from ...wishbone import wishbone_layout
-from .dmi import *
+from .dmi import DebugReg
 
 
 __all__ = ["BusError", "AccessSize", "DebugWishboneMaster"]