From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Apr 2019 04:36:15 +0000 (+0100)
Subject: disable write by default
X-Git-Tag: div_pipeline~2177^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fdb8d2f0d3e456191dbac16ff98b35e7d9d50644;p=soc.git

disable write by default
---

diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py
index fd2b3ff5..8cdcca12 100644
--- a/TLB/src/SetAssociativeCache.py
+++ b/TLB/src/SetAssociativeCache.py
@@ -228,9 +228,12 @@ class SetAssociativeCache():
         ]
 
         for mem in self.mem_array:
-            m.d.comb += mem.cset.eq(self.cset)
-            m.d.comb += mem.tag.eq(self.tag)
-            m.d.comb += mem.data_i.eq(self.data_i)
+            write_port = mem.w
+            m.d.comb += [mem.cset.eq(self.cset),
+                         mem.tag.eq(self.tag),
+                         mem.data_i.eq(self.data_i),
+                         write_port.en.eq(0), # default: disable write
+                        ]
 
         with m.If(self.enable):
             with m.Switch(self.command):