From: Luke Kenneth Casson Leighton Date: Sat, 29 Jun 2019 05:20:14 +0000 (+0100) Subject: use RVC reg encoding in VL Block X-Git-Tag: convert-csv-opcode-to-binary~4357 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fdd8891c6397b083e59103e3bc772181995f188c;p=libreriscv.git use RVC reg encoding in VL Block --- diff --git a/simple_v_extension/vblock_format_table.mdwn b/simple_v_extension/vblock_format_table.mdwn index fa74d1057..00e7178be 100644 --- a/simple_v_extension/vblock_format_table.mdwn +++ b/simple_v_extension/vblock_format_table.mdwn @@ -14,11 +14,10 @@ of the RISC-V ISA, is as follows: The VL/MAXVL/SubVL Block format: [[!table data=""" -31|30 | 29:28 | 27:22 | 21:17 | 16 | comment | -- | - | ----- | ------ | ------ | - | - | -0b00 || SubVL | VLdest | imm[4:0] | imm | VL, bits 16-21 | -0b01 || SubVL | MVLimm | VLreg | VLd | VLdest=t0,t1 | -0b10 || SubVL | VLdest | imm[4:0] | imm | VL & MVL, bits 16-21 | -0b11 || rsvd | rsvd | rsvd | rsv | reserved, all 0s | +31:30 | 29:28 | 27:22 | 21:19 | 18:16 | comment | +0b00 | SubVL | VLdest | imm[5:0] || VL set from imm | +0b01 | SubVL | MVLimm | rs1[2:0] | rd[2:0] | RVC reg format | +0b10 | SubVL | VLdest | imm[5:0] || VL & MVL set from imm| +0b11 | rsvd | rsvd | rsvd | rsv | reserved, all 0s | """]]