From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 14 Oct 2022 09:16:33 +0000 (+0100)
Subject: SVP64RMModeDecode detects Post-Inc LDST-imm mode
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fde459e6cfb70bf8c9272a943100534f60cf1b14;p=openpower-isa.git

SVP64RMModeDecode detects Post-Inc LDST-imm mode
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index ecf86de7..6e550c46 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1734,13 +1734,13 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
             ins_name = 'sv.%s' % ins_name
 
         # ld-immediate-with-pi mode redirects to ld-with-postinc
-        sv_mode = yield self.dec2.rm_dec.sv_mode
-        is_ldst_imm = sv_mode == SVMode.LDST_IMM.value
         ldst_imm_postinc = False
-        if is_ldst_imm and 'u' in ins_name and self.is_svp64_mode:
-            ins_name = ins_name.replace("u", "up")
-            ldst_imm_postinc = True
-            log("   enable ld/st postinc", ins_name)
+        if 'u' in ins_name and self.is_svp64_mode:
+            ldst_pi = yield self.dec2.rm_dec.ldst_postinc
+            if ldst_pi:
+                ins_name = ins_name.replace("u", "up")
+                ldst_imm_postinc = True
+                log("   enable ld/st postinc", ins_name)
 
         log("   post-processed name", dotstrp, ins_name, asmop)
 
diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index f1f86e65..69187500 100644
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -107,6 +107,8 @@ class SVP64RMModeDecode(Elaboratable):
         self.cr_2bit_in = Signal()  # bottom 2 bits of CR field
         self.ldst_ra_vec = Signal() # set when RA is vec, indicate Index mode
         self.ldst_imz_in = Signal() # set when LD/ST immediate is zero
+        self.ldst_postinc = Signal() # set when LD/ST immediate post-inc set
+        self.ldst_ffirst = Signal() # set when LD/ST immediate fail-first set
 
         ##### outputs #####
 
@@ -151,9 +153,11 @@ class SVP64RMModeDecode(Elaboratable):
         is_ldst = Signal()
         is_bc = Signal()
         is_cr = Signal()
+        is_ldstimm = Signal()
         comb += is_ldst.eq(self.fn_in == Function.LDST)
         comb += is_bc.eq(self.fn_in == Function.BRANCH) # XXX TODO use SV Mode
         comb += is_cr.eq(self.sv_mode == SVMode.CROP.value)
+        comb += is_ldstimm.eq(self.sv_mode == SVMode.LDST_IMM.value)
         mode2 = sel(m, mode, SVP64MODE.MOD2)
         cr = sel(m, mode, SVP64MODE.CR)
 
@@ -195,7 +199,11 @@ class SVP64RMModeDecode(Elaboratable):
             # combined arith / ldst decoding due to similarity
             with m.Switch(mode2):
                 with m.Case(0): # needs further decoding (LDST no mapreduce)
-                    with m.If(is_ldst):
+                    with m.If(is_ldstimm & mode[SVP64MODE.LDI_POST]):
+                        comb += self.mode.eq(SVP64RMMode.NORMAL)
+                        comb += self.ldst_postinc.eq(mode[SVP64MODE.LDI_PI])
+                        comb += self.ldst_ffirst.eq(mode[SVP64MODE.LDI_FF])
+                    with m.Elif(is_ldst):
                         comb += self.mode.eq(SVP64RMMode.NORMAL)
                     with m.Elif(mode[SVP64MODE.REDUCE]):
                         comb += self.mode.eq(SVP64RMMode.MAPREDUCE)
@@ -218,6 +226,10 @@ class SVP64RMModeDecode(Elaboratable):
             # extract zeroing
             with m.Switch(mode2):
                 with m.Case(0): # needs further decoding (LDST no mapreduce)
+                    with m.If(is_ldstimm &
+                                ~(self.ldst_postinc | self.ldst_ffirst)):
+                        # no predicate-zeroing in fail-first or postinc
+                        pass
                     with m.If(is_ldst):
                         # XXX TODO, work out which of these is most
                         # appropriate set both? or just the one?