From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 Sep 2023 17:15:35 +0000 (+0100)
Subject: indent text of lbzu description
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe0ab51b06694ac25b86afa56c991f745affafe3;p=openpower-isa.git

indent text of lbzu description
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 20252b28..3bedcb29 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -78,13 +78,13 @@ Pseudo-code:
 
 Description:
 
-Let the effective address (EA) be the sum (RA)+ D. The
-byte in storage addressed by EA is loaded into RT[56:63].
-RT[0:55] are set to 0.
+    Let the effective address (EA) be the sum (RA)+ D. The
+    byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
 
-EA is placed into register RA.
+    EA is placed into register RA.
 
-If RA=0 or RA=RT, the instruction form is invalid.
+    If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered: