From: whitequark Date: Mon, 2 Dec 2019 02:23:36 +0000 (+0000) Subject: hdl.ast: actually remove simulator commands. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe0b762f19c9976628652b48cb273c537921c639;p=nmigen.git hdl.ast: actually remove simulator commands. These were supposed to be removed in 7df70059, but I forgot. --- diff --git a/examples/basic/uart.py b/examples/basic/uart.py index 1279ae0..afbe487 100644 --- a/examples/basic/uart.py +++ b/examples/basic/uart.py @@ -103,44 +103,41 @@ if __name__ == "__main__": args = parser.parse_args() if args.action == "simulate": - from nmigen.hdl.ast import Passive - from nmigen.back import pysim - - with pysim.Simulator(uart, - vcd_file=open("uart.vcd", "w"), - gtkw_file=open("uart.gtkw", "w"), - traces=ports) as sim: - sim.add_clock(1e-6) - - def loopback_proc(): - yield Passive() - while True: - yield uart.rx_i.eq((yield uart.tx_o)) - yield - sim.add_sync_process(loopback_proc()) - - def transmit_proc(): - assert (yield uart.tx_ack) - assert not (yield uart.rx_rdy) - - yield uart.tx_data.eq(0x5A) - yield uart.tx_rdy.eq(1) - yield - yield uart.tx_rdy.eq(0) + from nmigen.back.pysim import Simulator, Passive + + sim = Simulator(uart) + sim.add_clock(1e-6) + + def loopback_proc(): + yield Passive() + while True: + yield uart.rx_i.eq((yield uart.tx_o)) yield - assert not (yield uart.tx_ack) + sim.add_sync_process(loopback_proc) - for _ in range(uart.divisor * 12): yield + def transmit_proc(): + assert (yield uart.tx_ack) + assert not (yield uart.rx_rdy) - assert (yield uart.tx_ack) - assert (yield uart.rx_rdy) - assert not (yield uart.rx_err) - assert (yield uart.rx_data) == 0x5A + yield uart.tx_data.eq(0x5A) + yield uart.tx_rdy.eq(1) + yield + yield uart.tx_rdy.eq(0) + yield + assert not (yield uart.tx_ack) - yield uart.rx_ack.eq(1) - yield - sim.add_sync_process(transmit_proc()) + for _ in range(uart.divisor * 12): yield + + assert (yield uart.tx_ack) + assert (yield uart.rx_rdy) + assert not (yield uart.rx_err) + assert (yield uart.rx_data) == 0x5A + + yield uart.rx_ack.eq(1) + yield + sim.add_sync_process(transmit_proc) + with sim.write_vcd("uart.vcd", "uart.gtkw"): sim.run() if args.action == "generate": diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py index 3bc9cb0..15d1d65 100644 --- a/nmigen/hdl/ast.py +++ b/nmigen/hdl/ast.py @@ -18,8 +18,8 @@ __all__ = [ "Signal", "ClockSignal", "ResetSignal", "UserValue", "Sample", "Past", "Stable", "Rose", "Fell", "Initial", - "Statement", "Assign", "Assert", "Assume", "Cover", "Switch", "Delay", "Tick", - "Passive", "ValueKey", "ValueDict", "ValueSet", "SignalKey", "SignalDict", + "Statement", "Assign", "Assert", "Assume", "Cover", "Switch", + "ValueKey", "ValueDict", "ValueSet", "SignalKey", "SignalDict", "SignalSet", ] @@ -1404,47 +1404,6 @@ class Switch(Statement): return "(switch {!r} {})".format(self.test, " ".join(case_reprs)) -@final -class Delay(Statement): - def __init__(self, interval=None, *, src_loc_at=0): - super().__init__(src_loc_at=src_loc_at) - self.interval = None if interval is None else float(interval) - - def _rhs_signals(self): - return ValueSet() - - def __repr__(self): - if self.interval is None: - return "(delay ε)" - else: - return "(delay {:.3}us)".format(self.interval * 1e6) - - -@final -class Tick(Statement): - def __init__(self, domain="sync", *, src_loc_at=0): - super().__init__(src_loc_at=src_loc_at) - self.domain = str(domain) - - def _rhs_signals(self): - return ValueSet() - - def __repr__(self): - return "(tick {})".format(self.domain) - - -@final -class Passive(Statement): - def __init__(self, *, src_loc_at=0): - super().__init__(src_loc_at=src_loc_at) - - def _rhs_signals(self): - return ValueSet() - - def __repr__(self): - return "(passive)" - - class _MappedKeyCollection(metaclass=ABCMeta): @abstractmethod def _map_key(self, key):