From: Jacob Lifshay Date: Tue, 16 May 2023 06:50:52 +0000 (-0700) Subject: fix fcvttg* overflow/FPSCR computation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe10201477688b499925baff207255901782f300;p=openpower-isa.git fix fcvttg* overflow/FPSCR computation --- diff --git a/openpower/isa/fpcvt.mdwn b/openpower/isa/fpcvt.mdwn index 27bd09a5..d25ba9cd 100644 --- a/openpower/isa/fpcvt.mdwn +++ b/openpower/isa/fpcvt.mdwn @@ -186,19 +186,23 @@ Pseudo-code: result_bfp <- bfp_CONVERT_FROM_SI64(result) default: # Unsigned 64-bit result_bfp <- bfp_CONVERT_FROM_UI64(result) + overflow <- 0 + if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then + overflow <- 1 # signals SO only when OE = 1 + vxcvi_flag <- 1 + xx_flag <- 0 + else if ¬bfp_COMPARE_EQ(src, result_bfp) then + xx_flag <- 1 if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN) if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI) if xx_flag = 1 then SetFX(FPSCR.XX) vx_flag <- vxsnan_flag | vxcvi_flag vex_flag <- FPSCR.VE & vx_flag - overflow <- 0 if vex_flag = 0 then RT <- result FPSCR.FPRF <- undefined(0b00000) FPSCR.FR <- inc_flag FPSCR.FI <- xx_flag - if IsNaN(src) | ¬bfp_COMPARE_EQ(src, result_bfp) then - overflow <- 1 # signals SO only when OE = 1 else FPSCR.FR <- 0 FPSCR.FI <- 0 @@ -296,19 +300,23 @@ Pseudo-code: result_bfp <- bfp_CONVERT_FROM_SI64(result) default: # Unsigned 64-bit result_bfp <- bfp_CONVERT_FROM_UI64(result) + overflow <- 0 + if IsNaN(src) | ¬bfp_COMPARE_EQ(rnd, result_bfp) then + overflow <- 1 # signals SO only when OE = 1 + vxcvi_flag <- 1 + xx_flag <- 0 + else if ¬bfp_COMPARE_EQ(src, result_bfp) then + xx_flag <- 1 if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN) if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI) if xx_flag = 1 then SetFX(FPSCR.XX) vx_flag <- vxsnan_flag | vxcvi_flag vex_flag <- FPSCR.VE & vx_flag - overflow <- 0 if vex_flag = 0 then RT <- result FPSCR.FPRF <- undefined(0b00000) FPSCR.FR <- inc_flag FPSCR.FI <- xx_flag - if IsNaN(src) | ¬bfp_COMPARE_EQ(src, result_bfp) then - overflow <- 1 # signals SO only when OE = 1 else FPSCR.FR <- 0 FPSCR.FI <- 0