From: Florent Kermarrec Date: Mon, 13 Jan 2020 13:39:45 +0000 (+0100) Subject: targets/genesys2: update self.register_sdram X-Git-Tag: 24jan2021_ls180~754 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe14b9cf86da1a7893e64978841cd707a23f6f55;p=litex.git targets/genesys2: update self.register_sdram --- diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 0a7e95a4..7bb495dc 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -61,7 +61,9 @@ class BaseSoC(SoCSDRAM): sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") sdram_module = MT41J256M16(self.clk_freq, "1:4") - self.register_sdram(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings) + self.register_sdram(self.ddrphy, + geom_settings = sdram_module.geom_settings, + timing_settings = sdram_module.timing_settings) # EthernetSoC --------------------------------------------------------------------------------------