From: Ron Dreslinski <rdreslin@umich.edu>
Date: Thu, 12 Oct 2006 18:21:25 +0000 (-0400)
Subject: Remove bus and top level parameters from cache
X-Git-Tag: m5_2.0_beta2~73^2~26
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe230ddb8ff2f3339ffaa20d30c01bb5b00185b6;p=gem5.git

Remove bus and top level parameters from cache

src/mem/cache/base_cache.hh:
    Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
    Remove top level parameters from the cache

--HG--
extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
---

diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 563b1ca8b..455e13d9c 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -212,10 +212,6 @@ class BaseCache : public MemObject
 
   protected:
 
-    /** True if this cache is connected to the CPU. */
-    bool topLevelCache;
-
-
     /** Stores time the cache blocked for statistics. */
     Tick blockedCycle;
 
@@ -337,7 +333,7 @@ class BaseCache : public MemObject
      */
     BaseCache(const std::string &name, Params &params)
         : MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
-          slaveRequests(0), topLevelCache(false),  blkSize(params.blkSize),
+          slaveRequests(0), blkSize(params.blkSize),
           missCount(params.maxMisses)
     {
         //Start ports at null if more than one is created we should panic
@@ -357,15 +353,6 @@ class BaseCache : public MemObject
         return blkSize;
     }
 
-    /**
-     * Returns true if this cache is connect to the CPU.
-     * @return True if this is a L1 cache.
-     */
-    bool isTopLevel()
-    {
-        return topLevelCache;
-    }
-
     /**
      * Returns true if the cache is blocked for accesses.
      */
@@ -561,8 +548,6 @@ class BaseCache : public MemObject
      */
     void respondToSnoop(Packet *pkt, Tick time)
     {
-//        assert("Implement\n" && 0);
-//	mi->respond(pkt,curTick + hitLatency);
         assert (pkt->needsResponse());
         CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
         reqMem->schedule(time);
@@ -585,15 +570,7 @@ class BaseCache : public MemObject
         {
             //This is where snoops get updated
             AddrRangeList dummy;
-//            if (!topLevelCache)
-//            {
-                cpuSidePort->getPeerAddressRanges(dummy, snoop);
-//            }
-//            else
-//            {
-//                snoop.push_back(RangeSize(0,-1));
-//            }
-
+            cpuSidePort->getPeerAddressRanges(dummy, snoop);
             return;
         }
     }
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 150abbe52..9db79b843 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -151,12 +151,7 @@ Cache(const std::string &_name,
       doCopy(params.doCopy), blockOnCopy(params.blockOnCopy),
       hitLatency(params.hitLatency)
 {
-//FIX BUS POINTERS
-//    if (params.in == NULL) {
-        topLevelCache = true;
-//    }
-//PLEASE FIX THIS, BUS SIZES NOT BEING USED
-        tags->setCache(this, blkSize, 1/*params.out->width, params.out->clockRate*/);
+    tags->setCache(this);
     tags->setPrefetcher(prefetcher);
     missQueue->setCache(this);
     missQueue->setPrefetcher(prefetcher);
@@ -397,7 +392,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
     Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
     BlkType *blk = tags->findBlock(pkt);
     MSHR *mshr = missQueue->findMSHR(blk_addr);
-    if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
+    if (coherence->hasProtocol()) { //@todo Move this into handle bus req
         //If we find an mshr, and it is in service, we need to NACK or invalidate
         if (mshr) {
             if (mshr->inService) {
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc
index 5ab706269..0efe393f9 100644
--- a/src/mem/cache/coherence/uni_coherence.cc
+++ b/src/mem/cache/coherence/uni_coherence.cc
@@ -68,14 +68,12 @@ UniCoherence::handleBusRequest(Packet * &pkt, CacheBlk *blk, MSHR *mshr,
     if (pkt->isInvalidate()) {
         DPRINTF(Cache, "snoop inval on blk %x (blk ptr %x)\n",
                 pkt->getAddr(), blk);
-        if (!cache->isTopLevel()) {
-            // Forward to other caches
-            Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
-            cshrs.allocate(tmp);
-            cache->setSlaveRequest(Request_Coherence, curTick);
-            if (cshrs.isFull()) {
-                cache->setBlockedForSnoop(Blocked_Coherence);
-            }
+        // Forward to other caches
+        Packet * tmp = new Packet(pkt->req, Packet::InvalidateReq, -1);
+        cshrs.allocate(tmp);
+        cache->setSlaveRequest(Request_Coherence, curTick);
+        if (cshrs.isFull()) {
+            cache->setBlockedForSnoop(Blocked_Coherence);
         }
     } else {
         if (blk) {