From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Jun 2018 14:57:03 +0000 (+0200)
Subject: Fix handling of signed memories
X-Git-Tag: yosys-0.8~64
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe2ee833e154691ef61cc72833b86e02266039a2;p=yosys.git

Fix handling of signed memories

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 40cbbc2a3..d9f0039af 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1300,6 +1300,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
 			cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
 
+			if (!sign_hint)
+				is_signed = false;
+
 			return RTLIL::SigSpec(wire);
 		}