From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 00:32:52 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
X-Git-Tag: working-ls180~881^2^2~145^2^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe3627523437cfddc069ec9e2c4607a1aaf9ce2e;p=yosys.git

Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
---

fe3627523437cfddc069ec9e2c4607a1aaf9ce2e
diff --cc tests/simple_abc9/abc9.v
index 58596d701,1844bac20..65eb01338
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@@ -268,14 -268,7 +268,19 @@@ assign o = { 1'b1, 1'bx }
  assign p = { 1'b1, 1'bx, 1'b0 };
  endmodule
  
- module abc9_test029(input clk, d, r, output reg q);
+ module abc9_test029(input clk1, clk2, input d, output reg q1, q2);
+ always @(posedge clk1) q1 <= d;
+ always @(negedge clk2) q2 <= q1;
+ endmodule
++
++module abc9_test030(input clk, d, r, output reg q);
 +always @(posedge clk or posedge r)
 +    if (r) q <= 1'b0;
 +    else q <= d;
 +endmodule
 +
- module abc9_test030(input clk, d, r, output reg q);
++module abc9_test031(input clk, d, r, output reg q);
 +always @(negedge clk or posedge r)
 +    if (r) q <= 1'b1;
 +    else q <= d;
 +endmodule
diff --cc tests/various/abc9.v
index e53dcdb21,30ebd4e26..85828bf30
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@@ -9,10 -9,3 +9,10 @@@ wire w
  unknown u(~i, w);
  unknown2 u2(w, o);
  endmodule
 +
- module abc9_test031(input clk, d, r, output reg q);
++module abc9_test032(input clk, d, r, output reg q);
 +initial q = 1'b0;
 +always @(negedge clk or negedge r)
 +    if (r) q <= 1'b0;
 +    else q <= d;
 +endmodule
diff --cc tests/various/abc9.ys
index f7a3f1fa0,5c9a4075d..81d0afd1b
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@@ -22,19 -22,3 +22,19 @@@ abc9 -lut 
  select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
  select -assert-count 1 t:unknown
  select -assert-none t:$lut t:unknown %% t: %D
 +
 +design -load read
- hierarchy -top abc9_test031
++hierarchy -top abc9_test032
 +proc
 +clk2fflogic
 +design -save gold
 +
 +abc9 -lut 4
 +check
 +design -stash gate
 +
 +design -import gold -as gold
 +design -import gate -as gate
 +
 +miter -equiv -flatten -make_assert -make_outputs gold gate miter
 +sat -seq 10 -verify -prove-asserts -show-ports miter