From: lkcl <lkcl@web>
Date: Sun, 24 Jan 2021 13:18:38 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~358
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe3b9035497c4d3712bf10ea30f64a9df461afa3;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index ddf350def..5f554a59f 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -291,12 +291,17 @@ LD/ST, will give that same capability, with far more flexibility.
 
 permutations of vector selection, to identify above asm-syntax:
 
-     imm(RA)  RT.v   RA.v   no stride allowed
+     imm(RA)  RT.v   RA.v   nonstrided
          sv.ld r#.v, ofst(r#2.v) -> r#2 is a vector of addresses
-     imm(RA)  RT.s   RA.v   no stride allowed
+     imm(RA)  RT.s   RA.v   nonstrided
          sv.ld r#, ofst(r#2.v) -> r#2 is a vector of addresses
-     imm(RA)  RT.v   RA.s   stride-select needed
+     imm(RA)  RT.v   RA.s   fixed stride: unit or element
          sv.ld r#.v, ofst(r#2).v -> the whole vector is at ofst+r#2
+           mem      0    1    2
+           destreg  r#   r#+1 r#+2
+         sv.ld/els r#.v, ofst(r#2).v -> the vector is at ofst*elidx+r#2
+           mem      0 ...    offs ...   offs*2
+           destreg  r#       r#+1       r#+2
      imm(RA)  RT.s   RA.s   not vectorised
          sv.ld r#, ofst(r#2)
 
@@ -309,6 +314,7 @@ TODO: indexed mode
      RA,RB    RT.v  RA.v  RB.s
         sv.ldx r#.v, r#2.v, r#3 -> vector of addresses
      RA,RB    RT.v  RA.s  RB.s
+        sv.ldx r#.v, r#2, r#3 -> VSPLAT mode
      RA,RB    RT.s  RA.v  RB.v
      RA,RB    RT.s  RA.s  RB.v
      RA,RB    RT.s  RA.v  RB.s