From: Jonathan Marek <jonathan@marek.ca>
Date: Thu, 19 Dec 2019 15:40:35 +0000 (-0500)
Subject: freedreno/ir3: fix vertex shader sysvals with pre_assign_inputs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe4a8df9a8e906fd8037027c898d35af718fa9ea;p=mesa.git

freedreno/ir3: fix vertex shader sysvals with pre_assign_inputs

The first pre_assign_inputs loop doesn't pre-assign sysvals, so skip the
second part for sysvals.

The sysvals don't need to be pre-assigned since the state for those isn't
shared between binning / nonbinning shaders.

Fixes assert failures in cases where the sysvals didn't end up in the same
registers for binning / nonbinning.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>
---

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 82149c98e60..b6fc39f2fb1 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -3495,7 +3495,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 		assert(in->opc == OPC_META_INPUT);
 		unsigned inidx = in->input.inidx;
 
-		if (pre_assign_inputs) {
+		if (pre_assign_inputs && !so->inputs[inidx].sysval) {
 			if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
 				compile_assert(ctx, in->regs[0]->num ==
 						so->nonbinning->inputs[inidx].regid);