From: Andrew Stubbs Date: Tue, 3 Mar 2020 23:16:13 +0000 (+0000) Subject: testsuite: adjustments for amdgcn X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe4b53b2e7e58d3bcf476a0a319b51a5a8c668a2;p=gcc.git testsuite: adjustments for amdgcn 2020-03-25 Andrew Stubbs gcc/testsuite/ * gcc.dg/vect/bb-slp-pr69907.c: Disable the dump scan for amdgcn. * lib/target-supports.exp (check_effective_target_vect_unpack): Add amdgcn. --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fe8460c7664..e750dcbc790 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-03-25 Andrew Stubbs + + * gcc.dg/vect/bb-slp-pr69907.c: Disable the dump scan for amdgcn. + * lib/target-supports.exp (check_effective_target_vect_unpack): + Add amdgcn. + 2020-03-25 Jakub Jelinek PR target/94292 diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c index 813b1af089a..fe52d18525a 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c @@ -19,5 +19,6 @@ void foo(unsigned *p1, unsigned short *p2) /* Disable for SVE because for long or variable-length vectors we don't get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD, - because there we can vectorize the epilogue using mixed vector sizes. */ -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { ! aarch64*-*-* } } } } */ + because there we can vectorize the epilogue using mixed vector sizes. + Likewise for AMD GCN. */ +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 10353af580a..3654e7bc232 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6717,7 +6717,8 @@ proc check_effective_target_vect_unpack { } { || ([istarget arm*-*-*] && [check_effective_target_arm_neon_ok] && [check_effective_target_arm_little_endian]) || ([istarget s390*-*-*] - && [check_effective_target_s390_vx]) }}] + && [check_effective_target_s390_vx]) + || [istarget amdgcn*-*-*] }}] } # Return 1 if the target plus current options does not guarantee