From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 May 2023 17:53:15 +0000 (+0100)
Subject: add quick preamble header
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fe4c1ea4e196bb84dc06fc081fa39c192ba64b0f;p=openpower-isa.git

add quick preamble header
---

diff --git a/src/openpower/cyclemodel/inorder.py b/src/openpower/cyclemodel/inorder.py
index 5d311c69..15281d24 100644
--- a/src/openpower/cyclemodel/inorder.py
+++ b/src/openpower/cyclemodel/inorder.py
@@ -1,5 +1,9 @@
 #!/usr/bin/env python3
 # An In-order cycle-accurate model of a Power ISA 3.0 hardware implementation
+# LGPLv3+
+# Funded by NLnet
+#
+# Bugs: https://bugs.libre-soc.org/show_bug.cgi?id=1039
 
 class RegisterWrite(set):
     """RegisterWrite: contains the set of Read-after-Write Hazards.